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公开(公告)号：US06788598B2
公开(公告)日：2004-09-07
申请号：US10448661
申请日：2003-05-30
申请人： Ming-Cheng Chang , Tie-Jiang Wu , Jeng-Ping Lin , Tse-Main Kuo , Hsu-Cheng Fan
发明人： Ming-Cheng Chang , Tie-Jiang Wu , Jeng-Ping Lin , Tse-Main Kuo , Hsu-Cheng Fan
IPC分类号： G11C700
CPC分类号： H01L27/10861 , G11C11/401 , G11C29/50 , G11C2029/5002 , G11C2029/5004 , H01L22/34 , H01L27/0207 , H01L27/10891 , H01L29/66181
摘要： A test key disposed on a scribe line of a wafer. The test key includes: two active areas disposed on the substrate; two first deep trench capacitors disposed on the substrate outside the two active areas; a rectangular active word line disposed on the substrate covering the first deep trench capacitors and the active areas; first and second passing word lines disposed on one side of the rectangular active word line and across the parallel active areas; a third passing word line disposed on another side of the rectangular active word line and across another end of the two active areas; two second deep trench capacitors disposed on the substrate under where the two first passing word lines overlap the two active areas; and four contacts disposed on the first active areas between the first and second word lines and between the third and the rectangular active word line.
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2.发明授权Test key and method for validating the doping concentration of buried layers within a deep trench capacitors 有权用于验证深沟槽电容器内掩埋层的掺杂浓度的测试键和方法公开(公告)号：US06812487B1
公开(公告)日：2004-11-02
申请号：US10601417
申请日：2003-06-23
申请人： Tie-Jiang Wu , Chien-Chang Huang , Yu-Wei Ting , Bo-Ching Jiang , Tse-Main Kuo
发明人： Tie-Jiang Wu , Chien-Chang Huang , Yu-Wei Ting , Bo-Ching Jiang , Tse-Main Kuo
IPC分类号： H01L2358
CPC分类号： H01L27/10861 , G11C11/401 , G11C29/50 , G11C2029/0403 , G11C2029/5002 , H01L22/34 , H01L29/66181
摘要： A test key for validating the doping concentration of buried layers within a deep trench capacitor. The test key is deposited in the scribe line region of a wafer. In the test key of the present invention, the deep trench capacitor is deposited in the scribe line region and has three buried layers of three doping concentrations. An isolation region is deposited in the capacitor, and a first plug, a second and a third plug are coupled to three positions of one buried layer of the three respectively. The present invention determines whether the doping concentration of buried layers within a deep trench capacitor is valid by a first resistance measured between the first plug and the second plug and a second resistance measured between the second plug and the third plug.
摘要翻译： 一种用于验证深沟槽电容器内埋层掺杂浓度的测试键。 测试键被沉积在晶片的划线区域中。 在本发明的测试键中，深沟槽电容器沉积在划线区域中并且具有三个掺杂浓度的三个掩埋层。 隔离区域沉积在电容器中，并且第一插头，第二和第三插头分别耦合到三个一个埋层的三个位置。 本发明通过在第一插头和第二插头之间测量的第一电阻以及在第二插头和第三插头之间测量的第二电阻来确定深沟槽电容器内的埋层的掺杂浓度是否有效。
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公开(公告)号：US20060128041A1
公开(公告)日：2006-06-15
申请号：US11339687
申请日：2006-01-26
IPC分类号： H01L21/66
CPC分类号： G03F9/7088 , G03F7/70633 , G03F7/70658 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.
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公开(公告)号：US07015050B2
公开(公告)日：2006-03-21
申请号：US10718612
申请日：2003-11-24
IPC分类号： H01L21/00
CPC分类号： G03F9/7088 , G03F7/70633 , G03F7/70658 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.
摘要翻译： 提供了用于确定在集成电路制造工艺中发生的不对准的测试结构和测试方法。 测试结构包括具有第一测试结构和第二测试结构的第一导电层，其上的电介质层和介电层上的第二导电层。 第二导电层包括在第一方向和第二方向上分别与第一测试结构和第二测试结构的一部分重叠的第三测试结构和第四测试结构。 第一方向与第二方向相反。 该方法包括测量第一和第二导电层之间的电特性以计算由不对准引起的偏移量的步骤。
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公开(公告)号：US07217581B2
公开(公告)日：2007-05-15
申请号：US11339687
申请日：2006-01-26
IPC分类号： H01L21/00
CPC分类号： G03F9/7088 , G03F7/70633 , G03F7/70658 , H01L22/34 , H01L2924/0002 , H01L2924/00
摘要： A test structure and a test method for determining misalignment occurring in integrated circuit manufacturing processes are provided. The test structure includes a first conductive layer having a first testing structure and a second testing structure, a dielectric layer thereon, and a second conductive layer on the dielectric layer. The second conductive layer includes a third testing structure and a fourth testing structure, which respectively overlap a portion of the first testing structure and the second testing structure in a first direction and a second direction. The first direction is opposite to the second direction. The method includes a step of measuring the electrical characteristic between the first and the second conductive layers to calculate an offset amount caused by the misalignment.
摘要翻译： 提供了用于确定在集成电路制造工艺中发生的不对准的测试结构和测试方法。 测试结构包括具有第一测试结构和第二测试结构的第一导电层，其上的电介质层和介电层上的第二导电层。 第二导电层包括在第一方向和第二方向上分别与第一测试结构和第二测试结构的一部分重叠的第三测试结构和第四测试结构。 第一方向与第二方向相反。 该方法包括测量第一和第二导电层之间的电特性以计算由不对准引起的偏移量的步骤。
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6.发明授权Device and method for detecting alignment of deep trench capacitors and active areas in DRAM devices 有权用于检测DRAM器件中深沟槽电容器和有源区域的对准的装置和方法公开(公告)号：US06838296B2
公开(公告)日：2005-01-04
申请号：US10448920
申请日：2003-05-29
申请人： Tie-Jiang Wu , Chien-Chang Huang , Bo-Ching Jiang , Yu-Wei Ting
发明人： Tie-Jiang Wu , Chien-Chang Huang , Bo-Ching Jiang , Yu-Wei Ting
IPC分类号： H01L21/8242 , H01L23/544 , H01L27/02 , H01L21/66
CPC分类号： H01L27/10861 , G11C11/401 , G11C2029/5002 , H01L22/34 , H01L27/0207 , H01L27/10867 , H01L27/1087
摘要： A test device and method for detecting alignment of deep trench capacitors and active areas in DRAM devices. A quadrilateral active area is disposed in the scribe line region, with four equilaterals and four vertex angles. Parallel first and second deep trench capacitors are disposed in the quadrilateral active area. The first deep trench capacitor has a first surface aligned with a second surface of the second deep trench capacitor. The first and second vertex angles of the four vertex angles have a diagonal line essentially perpendicular to the first and second surfaces. The first and second vertex angles are a predetermined distance from the first surface and the second surface respectively.
摘要翻译： 用于检测DRAM器件中深沟槽电容器和有源区域的对准的测试装置和方法。 四边形有源区域设置在划线区域，具有四个平衡和四个顶角。 平行的第一和第二深沟槽电容器设置在四边形有源区域中。 第一深沟槽电容器具有与第二深沟槽电容器的第二表面对准的第一表面。 四个顶角的第一和第二顶角具有基本上垂直于第一和第二表面的对角线。 第一和第二顶角分别与第一表面和第二表面预定的距离。
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公开(公告)号：US06891216B1
公开(公告)日：2005-05-10
申请号：US10664163
申请日：2003-09-17
IPC分类号： H01L21/334 , H01L21/8242 , H01L23/544 , H01L27/108 , H01L31/119 , H01L29/76 , H01L29/94
CPC分类号： H01L22/34 , H01L27/10829 , H01L27/10861 , H01L27/10873 , H01L27/10894 , H01L27/10897 , H01L29/66181
摘要： A test structure of a DRAM array includes a substrate. A transistor is formed on the substrate and has a first region and a second region as source/drain regions thereof. A deep trench capacitor is formed adjacent to the transistor and has a first width. A shallow trench isolation is formed in a top portion of the deep trench capacitor and has a second width. The second width is substantially shorter than the first one. A third region is formed adjacent to the deep trench capacitor. A first contact is formed on the substrate and contacts with the first region. A second contact is formed on the substrate and contacts with the third region.
摘要翻译： DRAM阵列的测试结构包括基板。 晶体管形成在衬底上并且具有第一区域和第二区域作为其源极/漏极区域。 深沟槽电容器形成在与晶体管相邻并且具有第一宽度。 浅沟槽隔离形成在深沟槽电容器的顶部，并且具有第二宽度。 第二宽度基本上比第一宽度短。 第三区域形成为与深沟槽电容器相邻。 第一触点形成在基板上并与第一区域接触。 第二触点形成在基板上并与第三区域接触。
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