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    Selective oxide trimming to improve metal T-gate transistor
    2.
    发明申请
    Selective oxide trimming to improve metal T-gate transistor 有权
    选择性氧化物修整以改善金属T型栅极晶体管

    公开(公告)号：US20060008973A1

    公开(公告)日：2006-01-12

    申请号：US10885855

    申请日：2004-07-07

    申请人： Timothy Phua ,  Kheng Tee ,  Liang Hsia

    发明人： Timothy Phua ,  Kheng Tee ,  Liang Hsia

    IPC分类号： H01L21/336 ,  H01L21/8238

    CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L21/28079 ,  H01L21/28123 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/66545

    摘要： A process to form a FET using a replacement gate. An example feature is that the PMOS sacrificial gate is made narrower than the NMOS sacrificial gate. The PMOS gate is implanted preferably with Ge to increase the amount of poly sacrificial gate that is oxidized to form PMOS spacers. The spacers are used as masks for the LDD Implant. The space between the PLLD regions is preferably larger that the space between the NLDD regions because of the wider PMOS spacers. The PLDD tends to diffuse readily more than NLDD due to the dopant being small and light (i.e. Boron). The wider spacer between the PMOS regions improves device performance by improving the short channel effects for PMOS. In addition, the oxidization of the sacrificial gates allows trimming of sacrificial gates thus extending the limitation of lithography. Another feature of an embodiment is that a portion of the initial pad oxide is removed, thus reducing the amount of undercut created during the channel oxide strip for the dummy gate process. This would improve on the gate overlap capacitance for a T-gate transistor. In a second embodiment, two metal gates with different work functions are formed.

    摘要翻译： 使用替换栅极形成FET的工艺。 一个示例特征是使PMOS牺牲栅极比NMOS牺牲栅极窄。 PMOS栅极优选用Ge注入以增加被氧化形成PMOS间隔物的多晶牺牲栅极的量。 间隔件用作LDD植入物的掩模。 由于较宽的PMOS间隔物，PLLD区之间的空间优选大于NLDD区之间的空间。 由于掺杂剂小且轻（即硼），PLDD容易从NLDD扩散更多。 PMOS区域之间的较宽间隔通过改善PMOS的短沟道效应来提高器件性能。 此外，牺牲栅极的氧化允许修剪牺牲栅极，从而延长了光刻的限制。 一个实施例的另一个特征是初始衬垫氧化物的一部分被去除，从而减少了在用于虚拟栅极处理的沟道氧化物带期间产生的底切的量。 这将提高T栅极晶体管的栅极重叠电容。 在第二实施例中，形成具有不同功函数的两个金属栅极。

    Wing gate transistor for integrated circuits
    3.
    发明授权
    Wing gate transistor for integrated circuits 有权
    用于集成电路的翼栅晶体管

    公开(公告)号：US07528445B2

    公开(公告)日：2009-05-05

    申请号：US11380378

    申请日：2006-04-26

    申请人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

    发明人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

    IPC分类号： H01L29/76 ,  H01L31/113 ,  H01L21/338

    CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.

    摘要翻译： 提供一种用于形成半导体器件的系统。 在半导体衬底上形成栅介电材料层，栅极材料层和盖材料层。 盖材料和栅极材料的一部分被加工以形成盖和门体部分。 门体部分上的翼部由栅极材料的剩余部分形成。 栅极主体部分的翼部的下方的栅介质材料被去除以形成栅极电介质。 使用门主体部分和机翼，在半导体衬底中形成轻掺杂的源极/漏极区域。

    WING GATE TRANSISTOR FOR INTEGRATED CIRCUITS
    4.
    发明申请
    WING GATE TRANSISTOR FOR INTEGRATED CIRCUITS 有权
    用于集成电路的栅极晶体管

    公开(公告)号：US20060180848A1

    公开(公告)日：2006-08-17

    申请号：US11380378

    申请日：2006-04-26

    申请人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

    发明人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

    IPC分类号： H01L21/336 ,  H01L29/76

    CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.

    摘要翻译： 提供一种用于形成半导体器件的系统。 在半导体衬底上形成栅介电材料层，栅极材料层和盖材料层。 盖材料和栅极材料的一部分被加工以形成盖和门体部分。 门体部分上的翼部由栅极材料的剩余部分形成。 栅极主体部分的翼部的下方的栅介质材料被去除以形成栅极电介质。 使用门主体部分和机翼，在半导体衬底中形成轻掺杂的源极/漏极区域。

    Method of forming wing gate transistor for integrated circuits
    5.
    发明授权
    Method of forming wing gate transistor for integrated circuits 失效
    形成用于集成电路的翼栅晶体管的方法

    公开(公告)号：US07056799B2

    公开(公告)日：2006-06-06

    申请号：US10820664

    申请日：2004-04-07

    申请人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

    发明人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

    IPC分类号： H01L21/336 ,  H01L21/425

    CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.

    摘要翻译： 提供一种用于形成半导体器件的系统。 在半导体衬底上形成栅介电材料层，栅极材料层和盖材料层。 盖材料和栅极材料的一部分被加工以形成盖和门体部分。 门体部分上的翼部由栅极材料的剩余部分形成。 栅极主体部分的翼部的下方的栅介质材料被去除以形成栅极电介质。 使用门主体部分和机翼，在半导体衬底中形成轻掺杂的源极/漏极区域。