公开(公告)号：US07528445B2

公开(公告)日：2009-05-05

申请号：US11380378

申请日：2006-04-26

申请人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

发明人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

IPC分类号： H01L29/76 ,  H01L31/113 ,  H01L21/338

CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.

摘要翻译： 提供一种用于形成半导体器件的系统。 在半导体衬底上形成栅介电材料层，栅极材料层和盖材料层。 盖材料和栅极材料的一部分被加工以形成盖和门体部分。 门体部分上的翼部由栅极材料的剩余部分形成。 栅极主体部分的翼部的下方的栅介质材料被去除以形成栅极电介质。 使用门主体部分和机翼，在半导体衬底中形成轻掺杂的源极/漏极区域。

公开(公告)号：US20060180848A1

公开(公告)日：2006-08-17

申请号：US11380378

申请日：2006-04-26

申请人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

发明人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

IPC分类号： H01L21/336 ,  H01L29/76

CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.

摘要翻译： 提供一种用于形成半导体器件的系统。 在半导体衬底上形成栅介电材料层，栅极材料层和盖材料层。 盖材料和栅极材料的一部分被加工以形成盖和门体部分。 门体部分上的翼部由栅极材料的剩余部分形成。 栅极主体部分的翼部的下方的栅介质材料被去除以形成栅极电介质。 使用门主体部分和机翼，在半导体衬底中形成轻掺杂的源极/漏极区域。

公开(公告)号：US07056799B2

公开(公告)日：2006-06-06

申请号：US10820664

申请日：2004-04-07

申请人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

发明人： Timothy Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

IPC分类号： H01L21/336 ,  H01L21/425

CPC分类号： H01L29/6653 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

摘要： A system is provided for forming a semiconductor device. Layers of gate dielectric material, gate material, and cap material are formed on a semiconductor substrate. The cap material and a portion of the gate material are processed to form a cap and a gate body portion. A wing on the gate body portion is formed from a remaining portion of the gate material. The gate dielectric material under a portion of the wing on the gate body portion is removed to form a gate dielectric. A lightly-doped source/drain region is formed in the semiconductor substrate using the gate body portion and the wing.

摘要翻译： 提供一种用于形成半导体器件的系统。 在半导体衬底上形成栅介电材料层，栅极材料层和盖材料层。 盖材料和栅极材料的一部分被加工以形成盖和门体部分。 门体部分上的翼部由栅极材料的剩余部分形成。 栅极主体部分的翼部的下方的栅介质材料被去除以形成栅极电介质。 使用门主体部分和机翼，在半导体衬底中形成轻掺杂的源极/漏极区域。

公开(公告)号：US07084025B2

公开(公告)日：2006-08-01

申请号：US10885855

申请日：2004-07-07

申请人： Timothy Wee Hong Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

发明人： Timothy Wee Hong Phua ,  Kheng Chok Tee ,  Liang Choo Hsia

IPC分类号： H01L21/8238 ,  H01L21/8234 ,  H01L21/305 ,  H01L21/4763

CPC分类号： H01L29/6653 ,  H01L21/26586 ,  H01L21/28079 ,  H01L21/28123 ,  H01L21/823842 ,  H01L21/82385 ,  H01L21/823857 ,  H01L29/495 ,  H01L29/66545

摘要： A process to form a FET using a replacement gate. An example feature is that the PMOS sacrificial gate is made narrower than the NMOS sacrificial gate. The PMOS gate is implanted preferably with Ge to increase the amount of poly sacrificial gate that is oxidized to form PMOS spacers. The spacers are used as masks for the LDD Implant. The space between the PLDD regions is preferably larger that the space between the NLDD regions because of the wider PMOS spacers. The PLDD tends to diffuse readily more than NLDD due to the dopant being small and light (i.e. Boron). The wider spacer between the PMOS regions improves device performance by improving the short channel effects for PMOS. In addition, the oxidization of the sacrificial gates allows trimming of sacrificial gates thus extending the limitation of lithography. Another feature of an embodiment is that a portion of the initial pad oxide is removed, thus reducing the amount of undercut created during the channel oxide strip for the dummy gate process. This would improve on the gate overlap capacitance for a T-gate transistor. In a second embodiment, two metal gates with different work functions are formed.

摘要翻译： 使用替换栅极形成FET的工艺。 一个示例特征是使PMOS牺牲栅极比NMOS牺牲栅极窄。 PMOS栅极优选用Ge注入以增加被氧化形成PMOS间隔物的多晶牺牲栅极的量。 间隔件用作LDD植入物的掩模。 PLDD区域之间的间隔优选比由于较宽的PMOS间隔物而在NLDD区域之间的间隔更大。 由于掺杂剂小且轻（即硼），PLDD容易从NLDD扩散更多。 PMOS区域之间的较宽间隔通过改善PMOS的短沟道效应来提高器件性能。 此外，牺牲栅极的氧化允许修剪牺牲栅极，从而延长了光刻的限制。 一个实施例的另一个特征是初始衬垫氧化物的一部分被去除，从而减少了在用于虚拟栅极处理的沟道氧化物带期间产生的底切的量。 这将提高T栅极晶体管的栅极重叠电容。 在第二实施例中，形成具有不同功函数的两个金属栅极。

公开(公告)号：US09318378B2

公开(公告)日：2016-04-19

申请号：US10923123

申请日：2004-08-21

申请人： Yeow Kheng Lim ,  Alex See ,  Tae Jong Lee ,  David Vigar ,  Liang Choo Hsia ,  Kin Leong Pey

发明人： Yeow Kheng Lim ,  Alex See ,  Tae Jong Lee ,  David Vigar ,  Liang Choo Hsia ,  Kin Leong Pey

IPC分类号： H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC分类号： H01L23/528 ,  H01L21/0276 ,  H01L21/288 ,  H01L21/3212 ,  H01L21/76802 ,  H01L21/76808 ,  H01L21/76816 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53295 ,  H01L23/562 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for slots in wide lines to reduce stress. An example embodiment method and structure for is an interconnect structure comprising: interconnect comprising a wide line. The wide line has a first slot. The first slot is spaced a first distance from a via plug so that the first slot relieves stress on the wide line and the via plug. The via plug can contact the wide line from above or below. Another example embodiment is a dual damascene interconnect structure comprising: an dual damascene shaped interconnect comprising a via plug, a first slot and a wide line. The wide line has the first slot. The first slot is spaced a first distance from the via plug so that the first slot relieves stress on the wide line and the via plug.

公开(公告)号：US08754447B2

公开(公告)日：2014-06-17

申请号：US12857543

申请日：2010-08-16

申请人： Jin Ping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jin Ping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L29/78

CPC分类号： H01L29/7848 ,  H01L21/26506 ,  H01L29/165 ,  H01L29/66636

摘要： A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.

摘要翻译： 一种晶体管器件结构，包括：由第一材料形成的衬底部分; 以及源区域，漏极区域和形成在所述衬底中的沟道区域，所述源极和漏极区域包括与所述第一材料不同的多个第二材料岛，所述岛被布置成在所述沟道区域中引起应变 底物。

公开(公告)号：US08716076B2

公开(公告)日：2014-05-06

申请号：US13190805

申请日：2011-07-26

申请人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Jinping Liu ,  Alex K H See ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L21/338

CPC分类号： H01L29/66636 ,  H01L21/823807 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/4958 ,  H01L29/4975 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66651 ,  H01L29/7848

摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.

摘要翻译： 具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。 开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。 在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。 外延材料限于开口，从而形成外延沟道。 在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。 通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

公开(公告)号：US08598031B2

公开(公告)日：2013-12-03

申请号：US12568658

申请日：2009-09-28

申请人： Fan Zhang ,  Xiaomei Bu ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

发明人： Fan Zhang ,  Xiaomei Bu ,  Jane Hui ,  Tae Jong Lee ,  Liang Choo Hsia

IPC分类号： H01L21/4763

CPC分类号： H01L23/5226 ,  H01L21/31127 ,  H01L21/31144 ,  H01L21/3212 ,  H01L21/76822 ,  H01L21/7684 ,  H01L21/76885 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a semiconductor device is presented. A substrate prepared with a dielectric layer formed thereon is provided. A sacrificial and a hard mask layer are formed on the dielectric layer. The dielectric, sacrificial and hard mask layers are patterned to form an interconnect opening. The interconnect opening is filled with a conductive material to form an interconnect. The conductive material is processed to produce a top surface of the conductive material that is substantially planar with a top surface of the sacrificial layer. The sacrificial layer is removed. The sacrificial layer protects the dielectric layer during processing of the conductive material.

公开(公告)号：US08177993B2

公开(公告)日：2012-05-15

申请号：US11556696

申请日：2006-11-05

申请人： Boon Meng Seah ,  Bei Chao Zhang ,  Raymond Joy ,  Shao Beng Law ,  John Sudijono ,  Liang Choo Hsia

发明人： Boon Meng Seah ,  Bei Chao Zhang ,  Raymond Joy ,  Shao Beng Law ,  John Sudijono ,  Liang Choo Hsia

IPC分类号： B44C1/22

CPC分类号： H01L21/67028 ,  H01L21/67051 ,  H01L21/6708

摘要： An first example method and apparatus for etching and cleaning a substrate comprises device with a first manifold and a second manifold. The first manifold has a plurality of nozzles for dispensing chemicals onto the substrate. The second manifold is attached to a vacuum source and/or a dry air/gas source. A second example embodiment is a wafer cleaning device and method that uses a manifold with capillary jet nozzles and a liquid capillary jet stream to clean substrates.

摘要翻译： 用于蚀刻和清洁衬底的第一示例性方法和装置包括具有第一歧管和第二歧管的装置。 第一歧管具有用于将化学品分配到基底上的多个喷嘴。 第二歧管连接到真空源和/或干燥空气/气体源。 第二示例性实施例是晶片清洁装置和方法，其使用具有毛细管喷嘴和液体毛细管喷流的歧管来清洁基底。

公开(公告)号：US20100019329A1

公开(公告)日：2010-01-28

申请号：US12220792

申请日：2008-07-28

申请人： Debora Chyiu Hyia Poon ,  Alex KH See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

发明人： Debora Chyiu Hyia Poon ,  Alex KH See ,  Francis Benistant ,  Benjamin Colombeau ,  Yun Ling Tan ,  Mei Sheng Zhou ,  Liang Choo Hsia

IPC分类号： H01L27/088 ,  H01L21/66 ,  G06F17/50

CPC分类号： H01L27/088 ,  H01L27/0211

摘要： A method (and semiconductor device) of fabricating a semiconductor device utilizes a thermal proximity correction (TPC) technique to reduce the impact of thermal variations during anneal. Prior to actual fabrication, a location of interest (e.g., a transistor) within an integrated circuit design is determined and an effective thermal area around the location is defined. Thermal properties of structures intended to be fabricated within this area are used to calculate an estimated temperature that would be achieved at the location of interest from a given anneal process. If the estimated temperature is below or above a predetermined target temperature (or range), TPC is performed. Various TPC techniques may be performed, such as the addition of dummy cells and/or changing dimensions of the structure to be fabricated at the location of interest (resulting in an modified thermally corrected design, to suppress local variations in device performance caused by thermal variations during anneal.

摘要翻译： 制造半导体器件的方法（和半导体器件）利用热接近校正（TPC）技术来减少退火期间热变化的影响。 在实际制造之前，确定集成电路设计中感兴趣的位置（例如，晶体管），并且定义该位置周围的有效热区。 用于在该区域内制造的结构的热性质被用于计算在给定的退火过程中在感兴趣的位置将实现的估计温度。 如果估计温度低于或高于预定目标温度（或范围），则执行TPC。 可以执行各种TPC技术，例如在感兴趣的位置添加虚拟单元和/或改变要制造的结构的尺寸（导致经修改的热校正设计，以抑制由热变化引起的器件性能的局部变化 在退火期间。