SYNCHRONOUS CLOCK STOP IN A MULTI NODAL COMPUTER SYSTEM
    1.
    发明申请
    SYNCHRONOUS CLOCK STOP IN A MULTI NODAL COMPUTER SYSTEM 有权
    多节点计算机系统中的同步时钟停止

    公开(公告)号:US20120005516A1

    公开(公告)日:2012-01-05

    申请号:US13170466

    申请日:2011-06-28

    IPC分类号: G06F1/12

    摘要: A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.

    摘要翻译: 提供一种计算机系统,其包括多个节点,其包括不同类型的芯片。 在每个节点中,一个芯片被配置为主芯片,其通过两个或更多个多点网络(例如,checkstop,clockrun)连接到一个或多个从芯片。 主芯片和从芯片连接到参考时钟,事件触发信息通过多点网络(checkstop,clockrun)发送到从芯片。 事件触发命令由主芯片在接收到请求时提交,内部偏移计数器用于在命令传播到芯片上的单元时调整接收周期和周期。 在运行中,偏移计数器由参考时钟同步。

    Synchronous clock stop in a multi nodal computer system
    3.
    发明授权
    Synchronous clock stop in a multi nodal computer system 有权
    多节点计算机系统中的同步时钟停止

    公开(公告)号:US08868960B2

    公开(公告)日:2014-10-21

    申请号:US13170466

    申请日:2011-06-28

    摘要: A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.

    摘要翻译: 提供一种计算机系统,其包括多个节点,其包括不同类型的芯片。 在每个节点中,一个芯片被配置为主芯片,其通过两个或更多个多点网络(例如,checkstop,clockrun)连接到一个或多个从芯片。 主芯片和从芯片连接到参考时钟,事件触发信息通过多点网络(checkstop,clockrun)发送到从芯片。 事件触发命令由主芯片在接收到请求时提交,内部偏移计数器用于在命令传播到芯片上的单元时调整接收周期和周期。 在运行中,偏移计数器由参考时钟同步。

    PALLET FOR HIGH TEMPERATURE PROCESSING
    5.
    发明申请
    PALLET FOR HIGH TEMPERATURE PROCESSING 审中-公开
    高温加工用托盘

    公开(公告)号:US20120121816A1

    公开(公告)日:2012-05-17

    申请号:US12954007

    申请日:2010-11-24

    IPC分类号: B65D19/38 C23C14/34

    摘要: A generally planar substrate pallet having an front, a back, and pair of sides. The distance between the front and the back and the distance between the sides are significantly longer than the thickness of the substrate pallet. The ratio of vertical deflection of the substrate pallet to the distance between the sides at temperatures used in high temperature processing systems relative to room temperature is less than 1%.

    摘要翻译: 具有前部,后部和一对侧面的大致平面的基板托盘。 前后的距离和两边之间的距离明显长于基板托盘的厚度。 在高温处理系统中使用的温度相对于室温的情况下,基板托盘的垂直偏转比与侧面之间的距离小于1%。