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公开(公告)号：US07308592B2
公开(公告)日：2007-12-11
申请号：US11056009
申请日：2005-02-11
申请人： Dietmar Schmunkamp , Andreas Wagner , Tobias Webel , Ulrich Weiss
发明人： Dietmar Schmunkamp , Andreas Wagner , Tobias Webel , Ulrich Weiss
CPC分类号： G06F11/1604 , G06F11/20
摘要： The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) (14) and the wiring (17) from there to multiple, PLL-(12) free clock chips (22) is provided. Instead of only one DCSC (14) and one single wiring (17), two of them (14-0, 14-1; 17-0, 17-1) are used combined with a further particular logic present on each clock chip (22), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.
摘要翻译： 本发明涉及计算机系统中的系统时钟。 特别地，它涉及具有增强的性能和可靠性程度的高端多处理器，多节点服务器计算机系统中的系统时钟以及用于在第一和第二时钟信号之间动态切换的方法，如果第一应用 失败。 提供了更多的冗余，即使是动态时钟切换电路（DCSC）（14）和布线（17），也可以是多个PLL-（12）空闲时钟芯片（22）。 而不是只有一个DCSC（14）和一个单个布线（17），它们中的两个（14 - 0，14 - 1，17 - 0，17 - 1）与每个时钟芯片上存在的另一个特定逻辑 22），其组合产生两个同步，微调的最小移位时钟信号，并总是选择第一个来获得控制时钟分配布线输出的FlipFlop。
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公开(公告)号：US20060184814A1
公开(公告)日：2006-08-17
申请号：US11056009
申请日：2005-02-11
申请人： Dietmar Schmunkamp , Andreas Wagner , Tobias Webel , Ulrich Weiss
发明人： Dietmar Schmunkamp , Andreas Wagner , Tobias Webel , Ulrich Weiss
IPC分类号： G06F1/06
CPC分类号： G06F11/1604 , G06F11/20
摘要： The present invention relates to system clocking in computer systems. In particular, it relates to system clocking in high-end multi-processor, multi-node server computer systems with an enhanced degree of performance and reliability and to a method for dynamically switching between a first and a second clock signal, if the first should fail. More redundancy even to the Dynamic Clock Switching Circuit (DCSC) (14) and the wiring (17) from there to multiple, PLL-(12) free clock chips (22) is provided. Instead of only one DCSC (14) and one single wiring (17), two of them (14-0, 14-1; 17-0, 17-1) are used combined with a further particular logic present on each clock chip (22), which in combination generate two synchronous, fine-tuned, minimum-shifted clock signals and select always the first of them to arrive at a FlipFlop controlling the output for clock distribution wiring.
摘要翻译： 本发明涉及计算机系统中的系统时钟。 特别地，它涉及具有增强的性能和可靠性程度的高端多处理器，多节点服务器计算机系统中的系统时钟以及用于在第一和第二时钟信号之间动态切换的方法，如果第一应用 失败。 提供了更多的冗余，即使是动态时钟切换电路（DCSC）（14）和布线（17），也可以是多个PLL-（12）空闲时钟芯片（22）。 而不是只有一个DCSC（14）和一个单个布线（17），它们中的两个（14 - 0，14 - 1，17 - 0，17 - 1）与每个时钟芯片上存在的另一个特定逻辑 22），其组合产生两个同步，微调的最小移位时钟信号，并总是选择第一个来获得控制时钟分配布线输出的FlipFlop。
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公开(公告)号：US5306959A
公开(公告)日：1994-04-26
申请号：US858252
申请日：1992-03-26
申请人： Guenter Knauft , Bernd Leppla , Dietmar Schmunkamp , Ulrich Weiss
发明人： Guenter Knauft , Bernd Leppla , Dietmar Schmunkamp , Ulrich Weiss
CPC分类号： H03K5/15
摘要： An electrical circuit for generating clock pulses for a multi-chip computer system which contains a clock generation chip and various logic circuit chips. The clock pulses used on the logic circuit chips are generated on the clock generation chip and are transferred to the logic circuit chips. For the generation of the clock pulses a so-called clock splitter circuit is provided on the clock generation circuit. This clock splitter generates two pulse strings out of a third pulse string which is derived from an oscillator. The clock splitter contains a number of gates and latches which have an impact on the throughput time of a pulse to run through the clock splitter, as well as on the skew of the two generated pulse strings. The invention provides an electrical circuit which has an improved throughput time and skew of the generated pulse strings.
摘要翻译： 一种用于为包含时钟生成芯片和各种逻辑电路芯片的多芯片计算机系统产生时钟脉冲的电路。 逻辑电路芯片上使用的时钟脉冲在时钟产生芯片上产生并被传送到逻辑电路芯片。 为了产生时钟脉冲，在时钟产生电路上提供所谓的时钟分配器电路。 该时钟分配器产生从振荡器导出的第三脉冲串中的两个脉冲串。 时钟分配器包含多个门和锁存器，这些门和锁存器对脉冲通过时钟分配器的吞吐量时间以及两个产生的脉冲串的偏斜有影响。 本发明提供了一种电路，其具有改善的生成时间和产生的脉冲串的偏斜。
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4.发明申请Method for Fault Tolerant Time Synchronization Mechanism in a Large Scaleable Multi-Processor Computer 失效大型可扩展多处理器计算机中容错时间同步机制的方法公开(公告)号：US20080215906A1
公开(公告)日：2008-09-04
申请号：US12116652
申请日：2008-05-07
IPC分类号： G06F1/12
CPC分类号： G06F11/1604 , G06F1/14 , G06F11/20
摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.
摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。
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5.发明授权Fault tolerant time synchronization mechanism in a scaleable multi-processor computer 失效可扩展多处理器计算机中的容错时间同步机制公开(公告)号：US07865758B2
公开(公告)日：2011-01-04
申请号：US12140028
申请日：2008-06-16
IPC分类号： G06F1/12
CPC分类号： G06F11/1604 , G06F1/14 , G06F11/20
摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.
摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。
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公开(公告)号：US08868960B2
公开(公告)日：2014-10-21
申请号：US13170466
申请日：2011-06-28
申请人： Tobias Bergmann , Ralf Ludewig , Tobias Webel , Ulrich Weiss
发明人： Tobias Bergmann , Ralf Ludewig , Tobias Webel , Ulrich Weiss
CPC分类号： G06F1/12 , G06F1/3237 , Y02D10/128
摘要： A computer system is provided which includes a plurality of nodes, which include chips of different types. In each node, one of the chips is configured as a master chip, which is connected to one or more slave chips via two or more multi-drop nets (e.g., checkstop, clockrun). The master chip and the slave chips are connected to a reference clock, and event triggering information is transmitted via the multi-drop nets (checkstop, clockrun) to the slave chips. Event trigger commands are submitted by the master chip when it receives a request, and internal offset counters are used to adjust both the receiving cycle and the cycle when the command is propagated to the units on the chips. In operation, the offset counters are synchronized by a reference clock.
摘要翻译： 提供一种计算机系统，其包括多个节点，其包括不同类型的芯片。 在每个节点中，一个芯片被配置为主芯片，其通过两个或更多个多点网络（例如，checkstop，clockrun）连接到一个或多个从芯片。 主芯片和从芯片连接到参考时钟，事件触发信息通过多点网络（checkstop，clockrun）发送到从芯片。 事件触发命令由主芯片在接收到请求时提交，内部偏移计数器用于在命令传播到芯片上的单元时调整接收周期和周期。 在运行中，偏移计数器由参考时钟同步。
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7.发明申请Fault Tolerant Time Synchronization Mechanism in a Scaleable Multi-Processor Computer 失效可扩展多处理器计算机中的容错时间同步机制公开(公告)号：US20080244300A1
公开(公告)日：2008-10-02
申请号：US12140028
申请日：2008-06-16
IPC分类号： G06F1/12
CPC分类号： G06F11/1604 , G06F1/14 , G06F11/20
摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.
摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。
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8.发明授权Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer 失效可扩展多处理器计算机中的容错时间同步机制的方法和装置公开(公告)号：US07761726B2
公开(公告)日：2010-07-20
申请号：US12116652
申请日：2008-05-07
IPC分类号： G06F1/12
CPC分类号： G06F11/1604 , G06F1/14 , G06F11/20
摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.
摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。
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9.发明授权Method and apparatus for fault tolerant time synchronization mechanism in a scaleable multi-processor computer 有权可扩展多处理器计算机中的容错时间同步机制的方法和装置公开(公告)号：US07487377B2
公开(公告)日：2009-02-03
申请号：US11054294
申请日：2005-02-09
IPC分类号： G06F13/42
CPC分类号： G06F11/1604 , G06F1/14 , G06F11/20
摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.
摘要翻译： 冗余时钟（TOD）振荡器在主振荡器路径内对准本地逻辑振荡器，并用于创建独立的步进同步信号。 步骤检验器验证并提供选择信号，以根据标准识别哪个TOD振荡器工作。 独立的步进同步信号被传送到几个同级芯片。 本地步进和同步信号被延迟到TOD寄存器，与同步芯片中的TOD寄存器几乎同步。 可以使用从属振荡器路径来选择在同级芯片中产生的时间信号，由此主振荡器路径被取消选择。 主控制寄存器组可以用于使用主振荡器路径来配置几个芯片中的哪一个是主芯片。 所有剩余的芯片都是从芯片。 拓扑的所有段都是冗余的。 多个可能的替代拓扑中的一个在二次控制寄存器集中被定义。 命令和TOD值以预定义的时间增量边界在结构上传递，以建立，恢复或维持所有芯片之间的同步。
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公开(公告)号：US20060179364A1
公开(公告)日：2006-08-10
申请号：US11054294
申请日：2005-02-09
申请人： Scott Swaney , Kenneth Ward , Tobias Webel , Ulrich Weiss , Matthias Woehrle
发明人： Scott Swaney , Kenneth Ward , Tobias Webel , Ulrich Weiss , Matthias Woehrle
IPC分类号： G06F11/00
CPC分类号： G06F11/1604 , G06F1/14 , G06F11/20
摘要： Redundant time-of-day (TOD) oscillators are aligned, within a master oscillator path, to local logic oscillator and used to create independent step-sync signals. A step checker validates and provides selection signals to identify which of the TOD oscillators operates according to a criterion. Independent step-sync signals are transmitted to several sibling chips. Local step and sync signals are delayed to arrive at TOD register nearly synchronous with TOD registers in sibling chips. A slave oscillator path may be used to select time signals generated in a sibling chip, whereby the master oscillator path is deselected. A primary control register set may be used to configure which among several chips is a master chip using the master oscillator path. All remaining chips are slave chips. All segments of the topology are redundant. One of multiple possible alternate topologies is defined in a secondary control register set. Commands and TOD values are passed on the fabric at predefined time increment boundaries to establish, restore, or maintain synchronization across all chips.
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