-
公开(公告)号：US11973904B2
公开(公告)日：2024-04-30
申请号：US17749146
申请日：2022-05-20
申请人： Shinji Sakaguchi , Tohru Kanno , Masamoto Nakazawa
发明人： Shinji Sakaguchi , Tohru Kanno , Masamoto Nakazawa
CPC分类号： H04N1/00236 , H04N1/32368
摘要： A signal processing device includes a data writing unit, a channel number converting unit, and a plurality of serial data transferring unit. The data writing unit is configured to write data of m channels into a memory. The channel number converting unit is configured to output the data read from the memory as data of n channels, where m is larger than n. The plurality of serial data transferring unit is configured to transfer the data of the n channels to a processing device in a subsequent stage.
-
公开(公告)号：US10250830B2
公开(公告)日：2019-04-02
申请号：US15447854
申请日：2017-03-02
申请人： Shinji Sakaguchi , Tohru Kanno
发明人： Shinji Sakaguchi , Tohru Kanno
摘要： A solid-state imaging device includes: a valid area including pixels that are not shielded from light; a first light-blocked area and a second light-blocked area each including pixels that are shielded from light; an analog-to-digital converting unit to convert the electric charge accumulated by the pixels belonging to the first light-blocked area, the valid area, and the second light-blocked area, to image data at a time; a signal reading unit to read light-blocked data obtained from the first light-blocked area and the second light-blocked area, and valid data obtained from the valid area, in units of pixels; a reference black level estimating unit to estimate a reference black level of the light-blocked data; and a level correction unit to correct, based on the estimated reference black level, a size of the valid data obtained simultaneously with the light-blocked data used in estimating the reference black level.
-
3.发明申请公开(公告)号：US20190028665A1
公开(公告)日：2019-01-24
申请号：US16029946
申请日：2018-07-09
申请人： Yuuya MIYOSHI , Tohru Kanno
发明人： Yuuya MIYOSHI , Tohru Kanno
IPC分类号： H04N5/378 , H04N5/3745
摘要： A photoelectric conversion device includes a pixel block including a plurality of pixels, a signal generating block, and a signal processing block. Each of the plurality of pixels includes a photoelectric conversion element to photoelectrically convert light striking the photoelectric conversion element into pixel data and output the pixel data; and a reset unit to reset electrical charge of the photoelectrically converted pixel data light and output a reset signal. The signal generating block includes a reference signal generator to generate a reference signal. The signal processing block performs correlated double sampling (CDS) on the reference signal to obtain correction data, and perform CDS on the pixel data and the reset signal to generate an output signal to correct the output signal with the correction data.
-
公开(公告)号：US20180254299A1
公开(公告)日：2018-09-06
申请号：US15893943
申请日：2018-02-12
申请人： Tohru KANNO
发明人： Tohru KANNO
IPC分类号： H01L27/146 , H01L23/522 , H01L23/528 , G01J1/44
CPC分类号： H01L27/14636 , G01J1/44 , H01L23/5225 , H01L23/5286 , H01L27/14603
摘要： An analog signal bus driving circuit includes a plurality of signal sources, a plurality of signal output amplifiers, a plurality of shield drive amplifiers, and a time-division control circuit. The plurality of signal sources generate a plurality of analog signals. The plurality of signal output amplifiers output the plurality of analog signals to at least one signal line. The plurality of shield drive amplifiers output the plurality of analog signals to a shield line. The shield line extends along the at least one signal line to at least partially surround the at least one signal line. The time-division control circuit sequentially drives the plurality of signal output amplifiers in a time-division manner to sequentially output the plurality of analog signals in a time-division manner from the plurality of signal sources to the at least one signal line.
-
公开(公告)号：US09986185B2
公开(公告)日：2018-05-29
申请号：US15447281
申请日：2017-03-02
申请人： Sho Kamezawa , Tohru Kanno , Yuuya Miyoshi
发明人： Sho Kamezawa , Tohru Kanno , Yuuya Miyoshi
IPC分类号： H04N5/369 , H03K17/687 , H04N5/378
CPC分类号： H04N5/3698 , H03K17/687 , H04N5/378
摘要： A semiconductor integrated circuit includes multiple signal processing circuits including a constant current source, a first bias source that generates first bias voltage, a second bias source that generates second bias voltage, a first bias circuit that supplies a first reference current to the first bias source, a second bias circuit that supplies a second reference current to the second bias source, a bias wiring that supplies the first bias voltage and the second bias voltage to a plurality of gates of a transistor that constructs the constant current source, a power source wiring that supplies a power source voltage to each of the first bias source, the second bias source, and the constant current source, a first voltage supplying source that applies a first power source voltage to the power source wiring, and a second voltage supplying that applies a second power source voltage to the power source wiring.
-
公开(公告)号：US20170264844A1
公开(公告)日：2017-09-14
申请号：US15447281
申请日：2017-03-02
申请人： Sho KAMEZAWA , Tohru KANNO , Yuuya MIYOSHI
发明人： Sho KAMEZAWA , Tohru KANNO , Yuuya MIYOSHI
IPC分类号： H04N5/369 , H04N5/378 , H03K17/687
CPC分类号： H04N5/3698 , H03K17/687 , H04N5/378
摘要： A semiconductor integrated circuit includes multiple signal processing circuits including a constant current source, a first bias source that generates first bias voltage, a second bias source that generates second bias voltage, a first bias circuit that supplies a first reference current to the first bias source, a second bias circuit that supplies a second reference current to the second bias source, a bias wiring that supplies the first bias voltage and the second bias voltage to a plurality of gates of a transistor that constructs the constant current source, a power source wiring that supplies a power source voltage to each of the first bias source, the second bias source, and the constant current source, a first voltage supplying source that applies a first power source voltage to the power source wiring, and a second voltage supplying that applies a second power source voltage to the power source wiring.
-
公开(公告)号：US20170251156A1
公开(公告)日：2017-08-31
申请号：US15434271
申请日：2017-02-16
申请人： Yuusuke KUDOH , Tohru KANNO
发明人： Yuusuke KUDOH , Tohru KANNO
IPC分类号： H04N5/378 , H04N5/359 , H01L27/146 , H04N9/04
CPC分类号： H04N5/378 , H01L27/14621 , H01L27/1463 , H01L27/14636 , H04N5/2176 , H04N5/359 , H04N5/361 , H04N9/045
摘要： An imaging device includes a pixel region in which a plurality of pixels and a plurality of charge-to-voltage conversion circuits are arranged in matrix. The pixels include photoelectric conversion elements that output charges in accordance with intensity of received light. The charge-to-voltage conversion circuits convert the charges output from the pixels into voltage signals. The pixel region includes an isolated region including isolated shaded pixels covered with a first shading metal of the same layer as a layer of wiring metals of the charge-to-voltage conversion circuits, and an isolated pixel that is not covered with the metal. All the pixels surrounding the isolated pixel in the isolated region are the isolated shaded pixels.
-
公开(公告)号：US20170244844A1
公开(公告)日：2017-08-24
申请号：US15411290
申请日：2017-01-20
申请人： Yuuya MIYOSHI , Tohru KANNO
发明人： Yuuya MIYOSHI , Tohru KANNO
CPC分类号： H04N1/00013 , H04N1/00907 , H04N1/0461 , H04N2201/0081 , H04N2201/0094
摘要： A solid-state imaging device includes a pixel circuit including a plurality of photoelectric conversion elements and configured to output a signal level and a reset level, an analog correlated double sampling (CDS) circuit connected to the pixel circuit and configured to perform correlated double sampling in an analog region based on the signal level and the reset level and output a result of the correlated double sampling, an analog-digital (AD) conversion circuit connected to the analog CDS circuit and configured to convert two different analog signals output from the analog CDS circuit into two digital signals, a signal processing circuit connected to the AD conversion circuit and configured to obtain a difference between the two different digital signals output from the AD conversion circuit; and a reference voltage generating circuit to output a first reference voltage that defines a clamp level of the analog CDS circuit.
-
公开(公告)号：US20140002151A1
公开(公告)日：2014-01-02
申请号：US14004967
申请日：2012-03-12
申请人： Yuji Watabe , Tohru Kanno
发明人： Yuji Watabe , Tohru Kanno
IPC分类号： H03L7/085
摘要： A fractional PLL circuit includes: a phase comparator for detecting a phase difference, and which outputs a controlled voltage; a voltage-controlled oscillator for generating and outputting an output clock signal; a phase-selection circuit for selecting any one of a predetermined number of phases into which one period of a clock of the output clock signal is equally divided, generating a phase-shift clock signal having a rising edge in the selected phase, and outputting the phase-shift clock signal to the phase comparator; and a phase controller for determining a phase of the rising edge of the phase-shift clock signal selected by the phase-selection circuit such that a period of the phase-shift clock signal is a length that is changed by a predetermined phase-shift amount from a period of the output clock signal, and controlling the phase-selection circuit so as to select the determined phase.
摘要翻译： 分数PLL电路包括：相位比较器，用于检测相位差，并输出受控电压; 用于产生和输出输出时钟信号的压控振荡器; 相位选择电路，用于选择输出时钟信号的时钟的一个周期被均分的预定数量的相位中的任一个，产生在所选择的相位中具有上升沿的相移时钟信号，并输出 相移时钟信号到相位比较器; 以及相位控制器，用于确定由相位选择电路选择的相移时钟信号的上升沿的相位，使得相移时钟信号的周期是改变预定相移量的长度 从输出时钟信号的周期开始，并且控制相位选择电路以便选择所确定的相位。
-
公开(公告)号：US08212908B2
公开(公告)日：2012-07-03
申请号：US12365510
申请日：2009-02-04
申请人： Masaki Nagase , Tohru Kanno
发明人： Masaki Nagase , Tohru Kanno
CPC分类号： H04N5/372 , H04N5/3765
摘要： A clock output from a quartz oscillator is input to a timing generator via a spread spectrum clock generator that spreads the spectrum of the clock. The clock is multiplexed by a phase locked loop to generate pixel clocks having the same frequency as a pixel frequency. The pixel clock is input to a delay locked loop, which generates a multi-layer clock by dividing each cycle of the pixel clock by 60. Clock generating units select a required phase from the multi-layer clock, thereby generating a timing signal. The phase, the pulse width, and the output period of the timing signal are controlled as desired by setting appropriate values to a register.
摘要翻译： 来自石英振荡器的时钟输出通过扩展时钟频谱的扩频时钟发生器输入到定时发生器。 时钟由锁相环复用，以生成与像素频率相同频率的像素时钟。 像素时钟被输入到延迟锁定环路，其通过将像素时钟的每个周期除以60来产生多层时钟。时钟产生单元从多层时钟中选择所需的相位，由此产生定时信号。 定时信号的相位，脉冲宽度和输出周期通过将适当值设置到寄存器来根据需要进行控制。
-
-
-
-
-
-
-
-
-
搜索结果
75 条记录 (耗时 0.026 秒)
