公开(公告)号：US07724606B2

公开(公告)日：2010-05-25

申请号：US11882117

申请日：2007-07-30

申请人： Tokuya Osawa ,  Masaru Haraguchi ,  Yoshikazu Morooka ,  Hiroshi Kinoshita

发明人： Tokuya Osawa ,  Masaru Haraguchi ,  Yoshikazu Morooka ,  Hiroshi Kinoshita

IPC分类号： G11C8/00

CPC分类号： G11C8/08 ,  G11C7/1066

摘要： A variable delay line receives and delays a data strobe signal transferred from a data source side in synchronization with a transfer data by a predetermined period, and produces a delayed data strobe signal and the non-delayed data strobe signal to a detector. The detector determines that a preamble period ends and effective data is transferred, when the delayed data strobe signal is at the L level at the time of rising of the non-delayed data strobe signal from the L level to the H level. According to a result of detection, an interface circuit unit takes in the transfer data and initializes a take-in address. The data strobe signal changes to a high-impedance state when a postamble ends. An influence of a glitch noise is avoided upon this change of the data strobe signal, and the data transfer can be executed fast and accurately.

摘要翻译： 可变延迟线接收并延迟从数据源侧与传送数据同步预定周期的数据选通信号，并将延迟数据选通信号和非延迟数据选通信号提供给检测器。 当非延迟数据选通信号从L电平上升到H电平时，当延迟的数据选通信号为L电平时，检测器确定前导码周期结束并传送有效数据。 根据检测结果，接口电路单元接收传送数据并初始化接收地址。 当后同步码结束时，数据选通信号变为高阻态。 数据选通信号的变化可以避免毛刺噪声的影响，可以快速准确地执行数据传送。

公开(公告)号：US06397363B1

公开(公告)日：2002-05-28

申请号：US09435622

申请日：1999-11-08

申请人： Hideshi Maeno ,  Tokuya Osawa

发明人： Hideshi Maeno ,  Tokuya Osawa

IPC分类号： G01R3128

CPC分类号： G11C29/40 ,  G11C29/44 ,  G11C29/848

摘要： A semiconductor integrated circuit device includes a memory circuit and a flag generator. The memory circuit is a circuit with a test circuit and includes a redundant circuit. The flag generator loads compared result information serially output from the memory circuit, and outputs flag signals if the compared result information includes at least one piece of mismatch information. This makes it possible to solve a problem of a conventional semiconductor integrated circuit device in that it takes a long time for carrying out a fault test of bits constituting the memory circuit.

摘要翻译： 半导体集成电路器件包括存储器电路和标志发生器。 存储器电路是具有测试电路并且包括冗余电路的电路。 标志发生器加载比较从存储器电路串行输出的结果信息，并且如果比较的结果信息包括至少一个失配信息，则输出标志信号。 这使得可以解决传统的半导体集成电路器件的问题在于，对构成存储器电路的位进行故障测试需要很长时间。

公开(公告)号：US5946247A

公开(公告)日：1999-08-31

申请号：US13062

申请日：1998-01-26

申请人： Tokuya Osawa ,  Hideshi Maeno

发明人： Tokuya Osawa ,  Hideshi Maeno

IPC分类号： G01R31/3185 ,  G11C29/08 ,  G11C29/32 ,  G11C7/00

CPC分类号： G11C29/08 ,  G01R31/318541 ,  G01R31/318566 ,  G11C29/32

摘要： In a small-size device, one input terminals of a plurality of AND circuits are connected in series. The other terminals of the plurality of AND circuits receive failure information held by a register circuit. Among the AND circuits, by changing values at the AND circuits which are connected in an output direction (i.e., most significant bit side) of an AND circuit receiving a failure bit and values at the AND circuits which are connected in an input direction (i.e., least significant bit side) of the AND circuit receiving the failure bit, a signal line associated with the failure bit is disconnected and signal lines are re-connected to adjacent signal lines including an extra line by selectors. Hence, a failure bit is compensated in a very simple structure.

摘要翻译： 在小型装置中，多个AND电路的一个输入端子串联连接。 多个AND电路的其他端子接收由寄存器电路保持的故障信息。 在AND电路中，通过改变在AND电路的输出方向（即，最高有效位侧）连接的AND电路中接收故障位的值和在输入方向连接的AND电路的值（即， ，最低有效位侧），与故障位相关联的信号线被断开，并且信号线被重新连接到包括选择器的额外线的相邻信号线。 因此，以非常简单的结构补偿故障位。

公开(公告)号：US5815512A

公开(公告)日：1998-09-29

申请号：US434999

申请日：1995-05-04

申请人： Tokuya Osawa ,  Hideshi Maeno

发明人： Tokuya Osawa ,  Hideshi Maeno

IPC分类号： G01R31/3185 ,  G11C29/08 ,  G11C29/32 ,  G01R31/28

CPC分类号： G11C29/08 ,  G01R31/318541 ,  G01R31/318566 ,  G11C29/32

摘要： In a small-size device, one input terminals of a plurality of AND circuits are connected in series. The other terminals of the plurality of AND circuits receive failure information held by a register circuit. Among the AND circuits, by changing values at the AND circuits which are connected in an output direction (i.e., most significant bit side) of an AND circuit receiving a failure bit and values at the AND circuits which are connected in an input direction (i.e., least significant bit side) of the AND circuit receiving the failure bit, a signal line associated with the failure bit is disconnected and signal lines are re-connected to adjacent signal lines including an extra line by selectors. Hence, a failure bit is compensated in a very simple structure.

公开(公告)号：US07535251B2

公开(公告)日：2009-05-19

申请号：US11852032

申请日：2007-09-07

申请人： Chikayoshi Morishima ,  Tokuya Osawa ,  Masaru Haraguchi ,  Yoshihiro Yamashita

发明人： Chikayoshi Morishima ,  Tokuya Osawa ,  Masaru Haraguchi ,  Yoshihiro Yamashita

IPC分类号： H03K17/16 ,  H03K19/003 ,  H03K19/094 ,  H03K19/0175 ,  H03K19/084 ,  G11C8/00

CPC分类号： H03K19/0005 ,  H03K19/018578

摘要： There is provided a semiconductor device including an output buffer circuit which reduces an area occupied by a circuit for impedance adjustment and allows high-speed impedance adjustment. In an impedance measuring circuit, the impedance values of reference transistors having the same sizes as those of a plurality of transistors composing the output buffer circuit which are equal in size are measured. An impedance code generating circuit outputs impedance codes corresponding to the impedance values of the reference transistors to an output buffer code generating circuit based on the result of the measurement from the impedance measuring circuit. The output buffer code generating circuit generates output buffer codes for adjusting the impedance of the output buffer circuit by performing an arithmetic operation process to provide an objective impedance based on the impedance codes.

摘要翻译： 提供了一种包括输出缓冲电路的半导体器件，其减少用于阻抗调整的电路占据的面积，并允许高速阻抗调节。 在阻抗测量电路中，测量与构成输出缓冲电路的多个晶体管尺寸相同尺寸的参考晶体管的尺寸相等的阻抗值。 基于来自阻抗测量电路的测量结果，阻抗代码产生电路将对应于参考晶体管的阻抗值的阻抗代码输出到输出缓冲器代码产生电路。 输出缓冲器代码产生电路通过执行算术运算处理产生用于调节输出缓冲器电路的阻抗的输出缓冲器代码，以提供基于阻抗代码的物镜阻抗。

公开(公告)号：US5960008A

公开(公告)日：1999-09-28

申请号：US768124

申请日：1996-12-17

申请人： Tokuya Osawa ,  Hideshi Maeno

发明人： Tokuya Osawa ,  Hideshi Maeno

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F11/22 ,  G11C29/12 ,  H01L21/822 ,  H01L27/04

CPC分类号： G01R31/318536

摘要： In a normal operation, a shift mode signal (SM) is set to "0" to propagate signals applied to "0"-input ends of selectors (10 to 12), i.e., outputs of a logic unit (80). In a logic scan test on logic units (80, 81), by setting a test-mode signal to "1", an ordinary scan test is performed with a scan path of simple configuration, having bits as much as write data and employing scan flip flops consisting of pairs of selectors (10 to 12) and flip flops (30 to 32) respectively. The flip flops used for writing in the normal operation can be also used as those used for the scan flip flops in the logic test. Thus, a configuration of the scan path to achieve excellent area-efficiency is provided.

摘要翻译： 在正常操作中，移位模式信号（SM）被设置为“0”以传播施加到选择器（10至12）的输入端的“0”的信号，即逻辑单元（80）的输出。 在对逻辑单元（80,81）的逻辑扫描测试中，通过将测试模式信号设置为“1”，以简单配置的扫描路径执行普通扫描测试，具有写入数据的位数和采用扫描 触发器分别由选择器（10至12）和触发器（30至32）组成。 在正常操作中用于写入的触发器也可以用作逻辑测试中用于扫描触发器的触发器。 因此，提供了实现优异的面积效率的扫描路径的结构。

公开(公告)号：US20080181047A1

公开(公告)日：2008-07-31

申请号：US12010674

申请日：2008-01-29

申请人： Masaru Haraguchi ,  Tokuya Osawa

发明人： Masaru Haraguchi ,  Tokuya Osawa

IPC分类号： G11C8/18

CPC分类号： G11C29/02 ,  G11C29/022 ,  G11C29/023

摘要： A semiconductor device in the present invention includes a DLL circuit which determines a phase shift amount, an arithmetic circuit which shifts the phase shift amount by a predetermined phase at test mode time, registers which set the phase shift amount, and a transmission circuit which shifts a phase to the set phase to transmit or receive a signal. The transmission circuit has a first phase shifter which shifts a first signal to the set phase, a first bidirectional buffer which loops back the first signal at the test mode time, a second phase shifter which phase-shifts the signal outputted from the first bidirectional buffer, a third phase shifter which phase-shifts a third signal, a second bidirectional buffer which loops back the third signal at the test mode time, a fourth phase shifter which phase-shifts the signal outputted from the second bidirectional buffer, and a FIFO which takes out an output signal of the second phase shifter or the fourth phase shifter.

摘要翻译： 本发明的半导体器件包括确定相移量的DLL电路，在测试模式时将相移量移位预定相位的运算电路，设定相移量的寄存器以及移相量的发送电路 一个阶段到设定阶段发送或接收一个信号。 传输电路具有第一移相器，其将第一信号移位到设定相位，第一双向缓冲器，以测试模式时间回送第一信号;第二移相器，其将从第一双向缓冲器输出的信号相移 第三移相器，其将第三信号相移，在测试模式时间使第三信号回路的第二双向缓冲器，使从第二双向缓冲器输出的信号相移的第四移相器;以及FIFO， 取出第二移相器或第四移相器的输出信号。

公开(公告)号：US06571364B1

公开(公告)日：2003-05-27

申请号：US09457530

申请日：1999-12-09

申请人： Hideshi Maeno ,  Tokuya Osawa

发明人： Hideshi Maeno ,  Tokuya Osawa

IPC分类号： G01R3128

CPC分类号： G11C29/44 ,  G01R31/318533

摘要： A semiconductor integrated circuit device with fault analysis function performs test operation for a memory circuit (such as a RAM) in which a comparison control circuit (6) generates a comparison control signal CCMP in order to select one or more memory cells in each memory cell group (34, 35, 36 and 37) corresponding to a single bit, a specified row, a specified bit, or a specified pattern, and then outputs the comparison control signal CCMP to scan flip flops (2, 3, 4 and 5) each including a comparator (292). The comparator (292) performs the comparison operation between data and expected values EXP and then outputs a comparison result only when address signals are input and data are red from memory cells, as the object of test, addressed by these address signals.

摘要翻译： 具有故障分析功能的半导体集成电路装置对比较控制电路（6）生成比较控制信号CCMP的存储器电路（例如RAM）进行测试操作，以选择每个存储单元中的一个或多个存储单元 对应于单个位，指定行，指定位或指定模式的组（34,35,36和37），然后将比较控制信号CCMP输出到扫描触发器（2,3,4和5） 每个包括比较器（292）。 比较器（292）执行数据和期望值EXP之间的比较操作，然后仅当输入地址信号并且从存储器单元中的数据为红色作为由这些地址信号寻址的测试对象时才输出比较结果。

公开(公告)号：US07983112B2

公开(公告)日：2011-07-19

申请号：US12010674

申请日：2008-01-29

申请人： Masaru Haraguchi ,  Tokuya Osawa

发明人： Masaru Haraguchi ,  Tokuya Osawa

IPC分类号： G11C8/16

CPC分类号： G11C29/02 ,  G11C29/022 ,  G11C29/023

摘要： A semiconductor device in the present invention includes a DLL circuit which determines a phase shift amount, an arithmetic circuit which shifts the phase shift amount by a predetermined phase at test mode time, registers which set the phase shift amount, and a transmission circuit which shifts a phase to the set phase to transmit or receive a signal. The transmission circuit has a first phase shifter which shifts a first signal to the set phase, a first bidirectional buffer which loops back the first signal at the test mode time, a second phase shifter which phase-shifts the signal outputted from the first bidirectional buffer, a third phase shifter which phase-shifts a third signal, a second bidirectional buffer which loops back the third signal at the test mode time, a fourth phase shifter which phase-shifts the signal outputted from the second bidirectional buffer, and a FIFO which takes out an output signal of the second phase shifter or the fourth phase shifter.

摘要翻译： 本发明的半导体器件包括确定相移量的DLL电路，在测试模式时将相移量移位预定相位的运算电路，设定相移量的寄存器以及移相量的发送电路 一个阶段到设定阶段发送或接收一个信号。 传输电路具有第一移相器，其将第一信号移位到设定相位，第一双向缓冲器，以测试模式时间回送第一信号;第二移相器，其将从第一双向缓冲器输出的信号相移 第三移相器，其将第三信号相移，在测试模式时间使第三信号回路的第二双向缓冲器，使从第二双向缓冲器输出的信号相移的第四移相器;以及FIFO， 取出第二移相器或第四移相器的输出信号。

公开(公告)号：US20100257324A1

公开(公告)日：2010-10-07

申请号：US12751810

申请日：2010-03-31

申请人： Tokuya Osawa ,  Masaru Haraguchi ,  Yoshikazu Morooka ,  Hiroshi Kinoshita

发明人： Tokuya Osawa ,  Masaru Haraguchi ,  Yoshikazu Morooka ,  Hiroshi Kinoshita

IPC分类号： G06F12/00

CPC分类号： G11C8/08 ,  G11C7/1066

摘要： A variable delay line receives and delays a data strobe signal transferred from a data source side in synchronization with a transfer data by a predetermined period, and produces a delayed data strobe signal and the non-delayed data strobe signal to a detector. The detector determines that a preamble period ends and effective data is transferred, when the delayed data strobe signal is at the L level at the time of rising of the non-delayed data strobe signal from the L level to the H level. According to a result of detection, an interface circuit unit takes in the transfer data and initializes a take-in address. The data strobe signal changes to a high-impedance state when a postamble ends. An influence of a glitch noise is avoided upon this change of the data strobe signal, and the data transfer can be executed fast and accurately.

摘要翻译： 可变延迟线接收并延迟从数据源侧与传送数据同步预定周期的数据选通信号，并将延迟数据选通信号和非延迟数据选通信号提供给检测器。 当非延迟数据选通信号从L电平上升到H电平时，当延迟的数据选通信号为L电平时，检测器确定前导码周期结束并传送有效数据。 根据检测结果，接口电路单元接收传送数据并初始化接收地址。 当后同步码结束时，数据选通信号变为高阻态。 数据选通信号的变化可以避免毛刺噪声的影响，可以快速准确地执行数据传送。