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    Process for the preparation of 1-(4-hydroxyphenyl)-2-(4-benzylpiperidino)-1-propanol and acid-addition salts thereof
    1.
    发明授权
    Process for the preparation of 1-(4-hydroxyphenyl)-2-(4-benzylpiperidino)-1-propanol and acid-addition salts thereof 失效
    1-（4-羟基苯基）-2-（4-苄基哌啶子基）-1-丙醇及其酸加成盐的制备方法

    公开(公告)号：US4377691A

    公开(公告)日：1983-03-22

    申请号：US213033

    申请日：1980-12-04

    申请人： Bompei Yasui ,  Tomohisa Miyamoto ,  Katsuyuki Hiraoka ,  Yoshitaka Sako

    发明人： Bompei Yasui ,  Tomohisa Miyamoto ,  Katsuyuki Hiraoka ,  Yoshitaka Sako

    IPC分类号： C07D211/14

    CPC分类号： C07D211/14

    摘要： A process for the preparation of 1-(4-hydroxyphenyl)-2-(4-benzylpiperidino)-1-propanol (i.e. ifenprodil) and acid-addition salts thereof, characterized by brominating 4'-hydroxypropiophenone in a single or mixed solvent selected from the group consisting of methanol, ethanol and a saturated aliphatic ether, removing hydrogen bromide formed in the course of the bromination, adding 4-benzylpyridine to the reaction mixture, heating the reaction mixture under reflux in a single or mixed solvent selected from the group consisting of methanol and ethanol, and then subjecting the resultant reaction mixture to catalytic reduction to form 1-(4-hydroxyphenyl)-2-(4-benzylpiperidino)-1-propanol hydrobromide in the reaction mixture. The end product (i.e. ifenprodil) can be obtained according to this process in a high yield of about 80% within 14 hours from the starting material in a single reaction container throughout the process, without introducing a protective benzyl group into the starting material prior to the bromination.

    摘要翻译： 制备1-（4-羟基苯基）-2-（4-苄基哌啶子基）-1-丙醇（即ifenprodil）及其酸加成盐的方法，其特征在于在选择的单一或混合溶剂中溴化4'-羟基苯丙酮 从甲醇，乙醇和饱和脂肪族醚组成的组中除去在溴化过程中形成的溴化氢，向反应混合物中加入4-苄基吡啶，将反应混合物在单一或混合溶剂中加热回流， 由甲醇和乙醇组成，然后使所得反应混合物进行催化还原以在反应混合物中形成1-（4-羟基苯基）-2-（4-苄基哌啶子基）-1-丙醇氢溴酸盐。 最终产品（即ifenprodil）可以在整个过程中在单一反应容器中从原料在14小时内以约80％的高产率获得，而不将保护性苄基基团在 溴化。

    Nonvolatile semiconductor memory device and method of operating a nonvolatile memory device
    4.
    发明授权
    Nonvolatile semiconductor memory device and method of operating a nonvolatile memory device 有权
    非易失性半导体存储器件以及非易失性存储器件的操作方法

    公开(公告)号：US08605512B2

    公开(公告)日：2013-12-10

    申请号：US13329372

    申请日：2011-12-19

    申请人： Shoichi Kawamura ,  Tomohisa Miyamoto

    发明人： Shoichi Kawamura ,  Tomohisa Miyamoto

    IPC分类号： G11C11/40

    CPC分类号： G11C16/3413 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3463 ,  G11C2216/14

    摘要： A nonvolatile memory device includes a memory cell array including a plurality of bitlines, a plurality of wordlines, and a plurality of memory cells. The memory device further includes a plurality of page buffers coupled to the respective bitlines of the memory cell array, each page buffer including a latch configured to store data to be written into and read from a memory cell coupled to a respective bitline of the memory cell array. The memory device further includes a control circuit configured to execute an over-program verify operation which includes detecting an over-programmed memory cell among the plurality of memory cells with reference to pass/fail data stored in the respective latches of the plurality of page buffers, and decreasing a threshold voltage of a detected over-programmed memory cell while maintaining a threshold voltage of memory cells which have not been detected as being over-programmed.

    摘要翻译： 非易失性存储器件包括包括多个位线，多个字线和多个存储器单元的存储单元阵列。 存储器装置还包括耦合到存储器单元阵列的相应位线的多个页缓冲器，每个页缓冲器包括锁存器，其被配置为存储要写入到耦合到存储器单元的相应位线的存储器单元中并从其读取的数据 数组。 该存储装置还包括控制电路，该控制电路被配置为执行过程编程验证操作，该操作包括参考存储在多个页缓冲器的相应锁存器中的通过/失败数据来检测多个存储器单元中的过度编程的存储器单元 并且在保持未被检测为过度编程的存储器单元的阈值电压的同时降低检测到的过度编程的存储单元的阈值电压。

    NON-VOLATILE MEMORY DEVICE
    5.
    发明申请
    NON-VOLATILE MEMORY DEVICE 有权
    非易失性存储器件

    公开(公告)号：US20130155773A1

    公开(公告)日：2013-06-20

    申请号：US13716511

    申请日：2012-12-17

    申请人： Tomohisa MIYAMOTO

    发明人： Tomohisa MIYAMOTO

    IPC分类号： G11C16/06

    CPC分类号： G11C16/06 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/26 ,  G11C16/32 ,  G11C16/3436

    摘要： A non-volatile memory device includes a memory cell array in which a plurality of bit lines intersect a plurality of word lines and a non-volatile memory cell is disposed at each intersection, a page buffer which is provided for each bit line and which includes a latch configured to store data to be written to a memory cell connected to a word line selected from among the plurality of word lines or data read from the memory cell, and a control circuit configured to control a data input time from the bit line to the page buffer and a data detection time of the latch according to a voltage level of a common source line connected to sources of the respective bit lines during an operation of reading data from the memory cell.

    摘要翻译： 非易失性存储器件包括存储单元阵列，其中多个位线与多条字线相交，并且非易失性存储单元设置在每个交叉点处，为每个位线提供的页缓冲器，其包括 锁存器，被配置为存储要写入到与从所述多个字线中选择的字线连接的存储器单元或从所述存储单元读取的数据的数据;以及控制电路，被配置为控制从所述位线到 所述页缓冲器和所述锁存器的数据检测时间根据在从所述存储器单元读取数据的操作期间连接到各个位线的源的公共源极线的电压电平。

    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING A NONVOLATILE MEMORY DEVICE
    6.
    发明申请
    NONVOLATILE SEMICONDUCTOR MEMORY DEVICE AND METHOD OF OPERATING A NONVOLATILE MEMORY DEVICE 有权
    非易失性半导体存储器件和操作非易失性存储器件的方法

    公开(公告)号：US20120155180A1

    公开(公告)日：2012-06-21

    申请号：US13329372

    申请日：2011-12-19

    申请人： Shoichi Kawamura ,  Tomohisa Miyamoto

    发明人： Shoichi Kawamura ,  Tomohisa Miyamoto

    IPC分类号： G11C16/34 ,  G11C16/04

    CPC分类号： G11C16/3413 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/3463 ,  G11C2216/14

    摘要： A nonvolatile memory device includes a memory cell array including a plurality of bitlines, a plurality of wordlines, and a plurality of memory cells. The memory device further includes a plurality of page buffers coupled to the respective bitlines of the memory cell array, each page buffer including a latch configured to store data to be written into and read from a memory cell coupled to a respective bitline of the memory cell array. The memory device further includes a control circuit configured to execute an over-program verify operation which includes detecting an over-programmed memory cell among the plurality of memory cells with reference to pass/fail data stored in the respective latches of the plurality of page buffers, and decreasing a threshold voltage of a detected over-programmed memory cell while maintaining a threshold voltage of memory cells which have not been detected as being over-programmed.

    摘要翻译： 非易失性存储器件包括包括多个位线，多个字线和多个存储器单元的存储单元阵列。 存储器装置还包括耦合到存储器单元阵列的相应位线的多个页缓冲器，每个页缓冲器包括锁存器，其被配置为存储要写入到耦合到存储器单元的相应位线的存储器单元中并从其读取的数据 数组。 该存储装置还包括控制电路，该控制电路被配置为执行过程编程验证操作，该操作包括参考存储在多个页缓冲器的相应锁存器中的通过/失败数据来检测多个存储器单元中的过度编程的存储器单元 并且在保持未被检测为过度编程的存储器单元的阈值电压的同时降低检测到的过度编程的存储单元的阈值电压。