公开(公告)号：US20060063335A1

公开(公告)日：2006-03-23

申请号：US10967657

申请日：2004-10-19

申请人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

发明人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

IPC分类号： H01L21/336 ,  H01L21/3205

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/872

摘要： A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.

公开(公告)号：US07365391B2

公开(公告)日：2008-04-29

申请号：US11528637

申请日：2006-09-28

申请人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido ,  Masato Mikawa

发明人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido ,  Masato Mikawa

IPC分类号： H01L31/00

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A semiconductor device having high withstand voltage is provided. An active groove 22a includes a long and narrow main groove part 26 and a sub groove part 27 connected to a longitudinal side surface of the main groove part, and a buried region 24 of a second conductivity type whose height is lower than the bottom surface of the base diffusion region 32a of the second conductivity type is provided on the bottom surface of the main groove part 26. An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32a is provided in the sub groove part 27. The buried region 24 is contacted to the base diffusion region 32a through the active groove filling region 25. Since one gate groove 83 is formed by the part above the buried region 24 in one active groove 22a, the gate electrode plugs 48 are not separated, which allows the electrode pattern to be simplified.

摘要翻译： 提供具有高耐压的半导体器件。 活动槽22a包括长而窄的主槽部26和与主槽部的纵向侧面连接的副槽部27以及高度低于底面的第二导电型的埋入区域24 第二导电类型的基底扩散区域32a设置在主槽部分26的底表面上。 在子槽部27中设置有与基底扩散区域32a相接触的第二导电类型的活动沟槽填充区域25。 埋入区域24通过有源沟槽填充区域25与基极扩散区域32a接触。 由于一个栅极沟槽83由一个有源槽22a中的掩埋区域24上方的部分形成，所以栅电极插塞48不分离，这允许电极图案被简化。

公开(公告)号：US07208375B2

公开(公告)日：2007-04-24

申请号：US10967657

申请日：2004-10-19

申请人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

发明人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

IPC分类号： H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/872

摘要： A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.

摘要翻译： 提供了一种提高晶体管耐破坏性的技术。 在本发明的晶体管中，填充区域的高度高于掩埋区域的高度，使得填充区域的耐受电压高于掩埋区域的耐受电压。 因此，由于在有源区域发生雪崩击穿，导致雪崩击穿电流流过具有大面积的有源区域，不会发生电流集中。 结果，增加了抵抗击穿的元件的坚固性。

公开(公告)号：US06876034B2

公开(公告)日：2005-04-05

申请号：US10607083

申请日：2003-06-27

申请人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

发明人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/12 ,  H01L29/47 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872 ,  H01L29/76

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/872

摘要： A semiconductor device having grooves uniformly filled with semiconductor fillers is provided. Both ends of each of narrow active grooves are connected to an inner circumferential groove surrounding the active grooves. The growth speed of semiconductor fillers on both ends of the active grooves becomes equal to that at their central portions. As a result, a semiconductor device having the active grooves filled with the semiconductor fillers at a uniform height is obtained.

摘要翻译： 提供了具有均匀填充有半导体填料的槽的半导体器件。 每个窄活动槽的两端连接到围绕有源槽的内周槽。 有源沟槽两端的半导体填料的生长速度与其中心部分的生长速度相等。 结果，获得了具有均匀高度填充有半导体填料的有源沟槽的半导体器件。

公开(公告)号：US07196376B2

公开(公告)日：2007-03-27

申请号：US11097998

申请日：2005-04-04

申请人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido

发明人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811

摘要： An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source electrode film 58a so as to have the same electric potential as a source region 64. When a reverse bias is applied between a base region 32a and a conductive layer 12, a reverse bias is also applied between the embedded region 24 and the conductive layer 12; and therefore, depletion layers spread out together and a withstanding voltage is increased.

摘要翻译： 活动沟槽填充区域23a保持在有源沟槽22的连接到位于栅极沟槽83下方的嵌入区域24的部分。 有源沟槽填充区域23a连接到源极电极膜58a以具有与源极区域64相同的电位。 当在基极区域32a和导电层12之间施加反向偏压时，在嵌入区域24和导电层12之间也施加反向偏压; 因此耗尽层一起展开并且耐受电压增加。

公开(公告)号：US20070045726A1

公开(公告)日：2007-03-01

申请号：US11528637

申请日：2006-09-28

申请人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido ,  Masato Mikawa

发明人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido ,  Masato Mikawa

IPC分类号： H01L29/94

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/66734 ,  H01L29/7397 ,  H01L29/7813

摘要： A semiconductor device having high withstand voltage is provided. An active groove 22a includes a long and narrow main groove part 26 and a sub groove part 27 connected to a longitudinal side surface of the main groove part, and a buried region 24 of a second conductivity type whose height is lower than the bottom surface of the base diffusion region 32a of the second conductivity type is provided on the bottom surface of the main groove part 26. An active groove filling region 25 of the second conductivity type in contact with the base diffusion region 32a is provided in the sub groove part 27. The buried region 24 is contacted to the base diffusion region 32a through the active groove filling region 25. Since one gate groove 83 is formed by the part above the buried region 24 in one active groove 22a, the gate electrode plugs 48 are not separated, which allows the electrode pattern to be simplified.

摘要翻译： 提供具有高耐压的半导体器件。 活动槽22a包括长而窄的主槽部26和与主槽部的纵向侧面连接的副槽部27以及高度低于底面的第二导电型的埋入区域24 第二导电类型的基底扩散区域32a设置在主槽部分26的底表面上。 在子槽部27中设置有与基底扩散区域32a相接触的第二导电类型的活动沟槽填充区域25。 埋入区域24通过有源沟槽填充区域25与基极扩散区域32a接触。 由于一个栅极沟槽83由一个有源槽22a中的掩埋区域24上方的部分形成，所以栅电极插塞48不分离，这允许电极图案被简化。

公开(公告)号：US20050224848A1

公开(公告)日：2005-10-13

申请号：US11097998

申请日：2005-04-04

申请人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido

发明人： Toru Kurosaki ,  Shinji Kunori ,  Mizue Kitada ,  Kosuke Ohshima ,  Hiroaki Shishido

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872 ,  H01L21/8242 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811

摘要： An active groove filled region 23a is kept at a portion of an active groove 22a connecting to an embedded region 24 positioned below a gate groove 83. The active groove filled region 23a connects to a source electrode film 58a so as to have the same electric potential as a source region 64. When a reverse bias is applied between a base region 32a and a conductive layer 12, a reverse bias is also applied between the embedded region 24 and the conductive layer 12; and therefore, depletion layers spread out together and a withstanding voltage is increased.

摘要翻译： 活动沟槽填充区域23a保持在有源沟槽22的连接到位于栅极沟槽83下方的嵌入区域24的部分。 有源沟槽填充区域23a连接到源极电极膜58a以具有与源极区域64相同的电位。 当在基极区域32a和导电层12之间施加反向偏压时，在嵌入区域24和导电层12之间也施加反向偏压; 因此耗尽层一起展开并且耐受电压增加。

公开(公告)号：US06906355B2

公开(公告)日：2005-06-14

申请号：US10677429

申请日：2003-10-03

申请人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

发明人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/12 ,  H01L29/47 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872 ,  H01L29/74

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/872

摘要： A semiconductor device having guard grooves uniformly filled with a semiconductor filler is provided. The four corners of a rectangular ring-shaped guard groove meet at right angles, and outer and inner auxiliary diffusion regions both rounded are connected to the four corners. Since the guard grooves do not have to be rounded, the plane orientation of a silicon single crystal exposed inside the guard grooves can be all {100}. Therefore, epitaxial growth in the guard grooves is uniformly carried out, and the grooves are filled with guard regions without defects.

摘要翻译： 提供了具有均匀填充有半导体填料的保护槽的半导体器件。 矩形环形保护槽的四个角部成直角相交，外部和内部辅助扩散区域均圆形连接到四个角。 由于保护槽不必是圆形的，所以在保护槽内暴露的硅单晶的平面取向可以全部为{100}。 因此，保护​​槽中的外延生长均匀地进行，并且沟槽被填充有无缺陷的防护区域。

公开(公告)号：US06841825B2

公开(公告)日：2005-01-11

申请号：US10449002

申请日：2003-06-02

申请人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

发明人： Toru Kurosaki ,  Hiroaki Shishido ,  Mizue Kitada ,  Shinji Kunori ,  Kosuke Ohshima

IPC分类号： H01L21/331 ,  H01L21/336 ,  H01L29/06 ,  H01L29/739 ,  H01L29/78 ,  H01L29/872 ,  H01L27/108

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/66348 ,  H01L29/7397 ,  H01L29/7811 ,  H01L29/872

摘要： A technique for improving a ruggedness of a transistor against breakdown is provided. In a transistor of the present invention, a height of filling regions is higher than that of buried regions, so that a withstanding voltage of the filling regions is higher than that of the buried regions. Therefore, since avalanche breakdown occurs in an active region, causing an avalanche breakdown current to flow through the active region having a large area, current concentration does not occur. As a result, a ruggedness of an element against breakdown is increased.

摘要翻译： 提供了一种提高晶体管耐破坏性的技术。 在本发明的晶体管中，填充区域的高度高于掩埋区域的高度，使得填充区域的耐受电压高于掩埋区域的耐受电压。 因此，由于在有源区域发生雪崩击穿，导致雪崩击穿电流流过具有大面积的有源区域，不会发生电流集中。 结果，增加了抵抗击穿的元件的坚固性。

公开(公告)号：US07573109B2

公开(公告)日：2009-08-11

申请号：US11528654

申请日：2006-09-28

申请人： Shinji Kunori ,  Hiroaki Shishido ,  Masato Mikawa ,  Kosuke Ohshima ,  Masahiro Kuriyama ,  Mizue Kitada

发明人： Shinji Kunori ,  Hiroaki Shishido ,  Masato Mikawa ,  Kosuke Ohshima ,  Masahiro Kuriyama ,  Mizue Kitada

IPC分类号： H01L29/76

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/1095 ,  H01L29/47 ,  H01L29/66712 ,  H01L29/7395 ,  H01L29/7802 ,  H01L29/7809 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device having high withstand strength against destruction. The semiconductor device 1 includes guard buried regions 44b of second conductivity type concentrically provided on a resistance layer 15 of first conductivity type and base diffusion regions 17a are provided inside of the guard buried region 44b and base buried regions 44a of the second conductivity type are provided on the bottom surface of the base diffusion regions 17a. A distance between adjacent base buried regions 44a at the bottom of the same base diffusion region 17a is Wm1, a distance between adjacent base buried regions 44a at the bottom of the different base diffusion regions 17a is Wm2, and a distance between the guard buried regions 44b is WPE. A ratio of an impurity quantity Q1 of the first conductivity type and an impurity quantity Q2 of the second conductivity type included inside the widthwise center of the innermost guard buried region 44b is 0.90

摘要翻译： 具有高抗破坏性能的半导体器件。 半导体器件1包括同心地设置在第一导电类型的电阻层15上的第二导电类型的保护掩埋区域44b，并且在保护掩埋区域44b的内侧设置有基极扩散区域17a，并且设置第二导电类型的基极掩埋区域44a 在基底扩散区域17a的底面上。 在相同的基底扩散区域17a的底部的相邻的基底掩埋区域44a之间的距离为Wm1，不同的基底扩散区域17a的底部的相邻的基底掩埋区域44a之间的距离为Wm2， 44b是WPE。 当Wm1