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    Digital delay circuit and digital PLL circuit with first and second delay units
    2.
    发明授权
    Digital delay circuit and digital PLL circuit with first and second delay units 失效
    数字延迟电路和具有第一和第二延迟单元的数字PLL电路

    公开(公告)号：US5969553A

    公开(公告)日：1999-10-19

    申请号：US985276

    申请日：1997-12-04

    申请人： Toshio Kishi ,  Yukihiko Shimazu

    发明人： Toshio Kishi ,  Yukihiko Shimazu

    IPC分类号： G11C11/407 ,  G11C11/4076 ,  H03K5/131 ,  H03K5/14 ,  H03L7/06 ,  H03L7/081 ,  H03L7/099

    CPC分类号： H03L7/0812 ,  Y10S331/02

    摘要： A digital delay circuit and a digital PLL circuit achieve reduction in size and power consumption. Each of a first delay line (301) and a second delay line (302) includes a plurality of delay elements. A control circuit (200) selects the delay element(s) included in a delay line (300), and a second clock signal (S11) passes only through the selected delay element(s). That is, the second clock signal (S11) does not pass through the non-selected delay element(s), which reduces power consumption.

    摘要翻译： 数字延迟电路和数字PLL电路实现了尺寸和功耗的降低。 第一延迟线（301）和第二延迟线（302）中的每一个包括多个延迟元件。 控制电路（200）选择延迟线（300）中包括的延迟元件，第二时钟信号（S11）仅通过所选择的延迟元件。 也就是说，第二时钟信号（S11）不通过未被选择的延迟元件，这降低了功耗。

    Semiconductor integrated circuit and semiconductor integrated circuit device
    3.
    发明授权
    Semiconductor integrated circuit and semiconductor integrated circuit device 失效
    半导体集成电路和半导体集成电路器件

    公开(公告)号：US5889429A

    公开(公告)日：1999-03-30

    申请号：US660865

    申请日：1996-06-10

    申请人： Souichi Kobayashi ,  Toshio Kishi

    发明人： Souichi Kobayashi ,  Toshio Kishi

    IPC分类号： H03K19/00 ,  G05F1/46 ,  H03K19/0175 ,  H03L7/06 ,  G05F1/10

    CPC分类号： G05F1/465

    摘要： A semiconductor integrated circuit which converts power-supply voltage applied from outside into optimum voltage for operating an internal circuit at the frequency of an internal clock in response to a multiplication control signal supplied to a PLL circuit from outside to generate the internal clock for operating the internal circuit by dividing a clock supplied from outside or by judging the cycle of an internal clock generated by dividing an external clock so as to supply the optimum voltage to the internal circuit.

    摘要翻译： 一种半导体集成电路，其将从外部施加的电源电压转换为最佳电压，以响应于从外部提供给PLL电路的乘法控制信号而以内部时钟的频率操作内部电路，以产生用于操作内部时钟的内部时钟 通过对从外部提供的时钟进行分频，或者判断由外部时钟分频而产生的内部时钟的周期，从而向内部电路提供最佳电压。