公开(公告)号：US5956520A

公开(公告)日：1999-09-21

申请号：US710902

申请日：1996-09-24

申请人： Toshio Kishi ,  Toru Shimizu ,  Shunichi Iwata ,  Shigeo Mizugaki ,  Yuichi Nakao ,  Toshio Doi

发明人： Toshio Kishi ,  Toru Shimizu ,  Shunichi Iwata ,  Shigeo Mizugaki ,  Yuichi Nakao ,  Toshio Doi

IPC分类号： G06F9/30 ,  G06F11/22 ,  G06F11/28 ,  G06F12/08 ,  G06F13/42 ,  G06F15/78 ,  G06F13/00

CPC分类号： G06F13/4213

摘要： An external bus I/F section has a function in which, when a bus access is requested by an instruction execution section, high-order several bits of a logical address generated by a CPU are outputted from an output terminal to the outside of a chip, as a space identifier for indicating which of an integrated ROM space, an integrated RAM space, and the external space is accessed by a currently executed program. A part of an address generated by the CPU is used so that the space which is accessed by the currently executed program is known from the outside in real time without requiring an external hardware.

摘要翻译： 外部总线I / F部分具有这样的功能，其中当由指令执行部分请求总线访问时，由CPU产生的逻辑地址的高位数位从输出端子输出到芯片的外部 作为用于指示由当前执行的程序访问的集成ROM空间，集成RAM空间和外部空间中的哪一个的空间标识符。 使用由CPU生成的地址的一部分，使得当前执行的程序访问的空间从外部实时获知，而不需要外部硬件。

公开(公告)号：US5323175A

公开(公告)日：1994-06-21

申请号：US822483

申请日：1992-01-17

申请人： Toshio Doi ,  Shigeo Mizugaki ,  Yoshinori Hayashi

发明人： Toshio Doi ,  Shigeo Mizugaki ,  Yoshinori Hayashi

IPC分类号： G06F3/153 ,  G06F12/04 ,  G09G5/22 ,  G09G5/24 ,  G09G1/14

CPC分类号： G09G5/24

摘要： In order to reduce the capacity of a character ROM without reducing the character information, n-bit bit pattern data and sequence data having information necessary for composing n-bit m components are stored in first memory means (character ROM). Second memory means has addresses corresponding to each display position on the screen and holds addresses for the first memory means as a data. In accordance with the address from the second memory means and the sequence data from the first memory means, address modifying means produces an address of a scanning line with respect to pertinent character for the first memory means. According to this address, the bit pattern data is read out from the first memory means.

摘要翻译： 为了在不减少字符信息的情况下降低字符ROM的容量，将具有组成n位m分量所需的信息的n位位模式数据和序列数据存储在第一存储装置（字符ROM）中。 第二存储器装置具有与屏幕上的每个显示位置相对应的地址，并且将第一存储器装置的地址保存为数据。 根据来自第二存储器装置的地址和来自第一存储装置的序列数据，地址修改装置产生关于第一存储装置的相关字符的扫描行的地址。 根据该地址，从第一存储装置读出位模式数据。

公开(公告)号：US4639892A

公开(公告)日：1987-01-27

申请号：US556387

申请日：1983-11-30

申请人： Shigeo Mizugaki ,  Tsunenori Umeki

发明人： Shigeo Mizugaki ,  Tsunenori Umeki

IPC分类号： G11C17/00 ,  G11C17/12 ,  G11C17/16 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/78 ,  G11C11/40

CPC分类号： G11C17/16

摘要： A semiconductor read-only memory device includes first and second MOS field effect mode transistors (MOSFET) as memory elements storing either one of binary values of binary information. The first MOSFET has such a relatively long effective gate length that it becomes conductive upon receipt of a first relatively high gate voltage applied thereto as a memory selection signal and becomes non-conductive upon receipt of a second relatively low gate voltage. The second MOSFET, on the other hand, has such a relatively short effective gate length that it becomes conductive whether the first or second gate voltage is applied thereto.

摘要翻译： 半导体只读存储器件包括作为存储二进制信息的二进制值之一的存储器元件的第一和第二MOS场效应晶体管（MOSFET）。 第一MOSFET具有这样相当长的有效栅极长度，其在接收到施加到其上的第一相对高的栅极电压时变为导通，作为存储器选择信号，并且在接收到第二相对低的栅极电压时变得不导通。 另一方面，第二MOSFET具有这样的相对较短的有效栅极长度，无论其施加第一或第二栅极电压，其都变得导通。

公开(公告)号：US5487157A

公开(公告)日：1996-01-23

申请号：US248793

申请日：1994-05-25

申请人： Shigeo Mizugaki

发明人： Shigeo Mizugaki

IPC分类号： G06F15/78 ,  G06F9/26 ,  G06F9/32

CPC分类号： G06F9/268

摘要： To speed up switch between the use of a data bus by CPU for reading and writing data and the use of the data bus for refreshing a DRAM in a microcomputer having a DRAM refresh function, a terminal count signal 20 which is activated by a refresh timer 9 when a memory subsystem 8 composed of an external DRAM needs to be refreshed is directly input into a microinstruction sequencer 15 for controlling the order of executing a set of microinstructions of CPU 2. Therefore, CPU 2 can interrupt the execution of a set of microinstructions to execute a refresh cycle and can resume the execution of the interrupted set of microinstructions as controlled by the microinstruction sequencer 15 after the refresh cycle is finished.

摘要翻译： 为了加速在CPU使用数据总线之间进行数据读取和写入数据的切换，以及使用数据总线来刷新具有DRAM刷新功能的微型计算机中的DRAM，由刷新定时器激活的终端计数信号20 如图9所示，当由外部DRAM构成的存储器子系统8需要刷新时，直接输入到微指令定序器15中，用于控制执行CPU2微指令集的顺序。因此，CPU2可以中断一组微指令的执行 执行刷新周期并且可以在刷新周期完成之后恢复由微指令定序器15控制的中断的微指令集的执行。

公开(公告)号：US5394533A

公开(公告)日：1995-02-28

申请号：US869699

申请日：1992-04-16

申请人： Toshio Doi ,  Shigeo Mizugaki

发明人： Toshio Doi ,  Shigeo Mizugaki

IPC分类号： G06F12/08 ,  G06F12/00 ,  G06F12/14

CPC分类号： G06F12/0888 ,  G06F12/0864

摘要： A data cache, for use in a memory having an address space including tag addresses for identifying blocks of storage locations and a set of select addresses for identifying storage locations in a block, includes a set select decoder that decodes only a subset of said set of select addresses that identify sub-blocks of storage locations located at the upper and lower boundaries of a block. Thus, data in storage locations accessed by addresses near block boundaries which have a high number of bit transitions is registered to the cache so that the high number of bit transitions does not have to be driven on an external bus so that noise is reduced.

摘要翻译： 一种数据高速缓存，用于具有地址空间的存储器，该存储器包括用于标识存储位置的块的标签地址和用于识别块中的存储位置的一组选择地址，所述集合选择解码器仅对所述一组 选择标识位于块的上边界和下边界的存储位置的子块的地址。 因此，通过具有高数量位转换的块边界附近的地址访问的存储位置中的数据被登记到高速缓存，使得不必在外部总线上驱动高数量的位转换，从而降低噪声。

公开(公告)号：US5392435A

公开(公告)日：1995-02-21

申请号：US129008

申请日：1993-09-29

申请人： Norio Masui ,  Shigeo Mizugaki

发明人： Norio Masui ,  Shigeo Mizugaki

IPC分类号： G06F1/04 ,  G06F1/32 ,  G06F9/46 ,  G06F9/48 ,  G06F13/24 ,  G06F15/78 ,  G06F1/08

CPC分类号： G06F1/3215 ,  G06F1/324 ,  G06F13/24 ,  Y02B60/1217

摘要： A microcomputer provided with improved interrupt handling. The frequency of a clock signal supplied to the central processing unit is increased to shorten the interrupt holding time when relatively many interrupts are occurring. When few interrupts are occurring, the frequency of the clock signal is decreased thereby reducing power consumption. The invention includes a holding factors register for storing the number of interrupt factors being held by an interrupt controller and an interrupt nesting counter for storing the number of nested interrupts in the central processing unit. The numbers stored in the holding factors register and interrupt nesting counter are compared to preset numbers. A clock control circuit changes the frequency of the system clock signal in accordance with the comparison result thereby changing the frequency of the clock signal depending on the number of occurrences of interrupts.

摘要翻译： 微机提供改进的中断处理。 当发生相当多的中断时，提供给中央处理单元的时钟信号的频率增加以缩短中断保持时间。 当发生少量中断时，时钟信号的频率降低，从而降低功耗。 本发明包括一个用于存储由中断控制器保持的中断因数的保持因子寄存器和用于存储中央处理单元中的嵌套中断次数的中断嵌套计数器。 存储在保持因子寄存器和中断嵌套计数器中的数字与预设数字进行比较。 时钟控制电路根据比较结果改变系统时钟信号的频率，从而根据中断的发生次数改变时钟信号的频率。

公开(公告)号：US5303354A

公开(公告)日：1994-04-12

申请号：US909868

申请日：1992-07-07

申请人： Ryohei Higuchi ,  Shigeo Mizugaki

发明人： Ryohei Higuchi ,  Shigeo Mizugaki

IPC分类号： G06F7/00 ,  G06F9/30 ,  G06F9/315 ,  G06F9/38 ,  G06F15/78 ,  G06F9/00

CPC分类号： G06F9/30032 ,  G06F9/30141

摘要： Data is transferred directly from a source register in a register file connected to a data bus from a destination register in the register file, through a read data latch, a data bus bypass mechanism, and a write data latch. Since the data bus is bypassed, the update of a data pointer is possible concurrently with the transfer of data between the source register and the destination register.

摘要翻译： 数据通过读数据锁存器，数据总线旁路机制和写数据锁存器直接从寄存器文件中的目的地寄存器中连接到数据总线的寄存器文件中的源寄存器传送。 由于数据总线被旁路，数据指针的更新可能与源寄存器和目标寄存器之间的数据传输同时进行。

公开(公告)号：US4937782A

公开(公告)日：1990-06-26

申请号：US142111

申请日：1988-01-11

申请人： Shigeo Mizugaki ,  Toyokatsu Nakajima ,  Kikuo Muramatsu

发明人： Shigeo Mizugaki ,  Toyokatsu Nakajima ,  Kikuo Muramatsu

IPC分类号： G06F9/30 ,  G06F1/04 ,  G06F15/78 ,  H03K21/38

CPC分类号： H03K21/38

摘要： A counter control method according to the present invention comprising the steps of:(a) allocating switching information corresponding to counters in need of being simultaneously started among switching information each serving to drive a plurality of switching means, to an address (c) of memory means to which operation control means is accessible at a time, and(b) driving said switching means using said switching information so allocated to thereby start said plurality of the counters.

摘要翻译： 根据本发明的计数器控制方法包括以下步骤：（a）将与驱动多个切换装置的切换信息中需要同时开始的计数器相对应的切换信息分配给存储器的地址（c） 一种操作控制装置一次可访问的装置，以及（b）使用所分配的切换信息驱动所述切换装置，从而启动所述多个计数器。

公开(公告)号：US5669012A

公开(公告)日：1997-09-16

申请号：US720455

申请日：1996-09-30

申请人： Toru Shimizu ,  Shunichi Iwata ,  Toshio Doi ,  Shigeo Mizugaki

发明人： Toru Shimizu ,  Shunichi Iwata ,  Toshio Doi ,  Shigeo Mizugaki

IPC分类号： G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/308 ,  G06F9/315 ,  G06F9/34 ,  G06F9/35

CPC分类号： G06F9/30018 ,  G06F9/30032 ,  G06F9/30167

摘要： A data processor being provided with a microdecoder which decodes instruction codes comprising two operation code parts, a source operand specifying part and a destination operand specifying part, wherein an optional bit area of source data (a register of a general register file or a memory) is inserted in an optional bit area (determined by the value of the first operation code part) of a destination register according to the decoding result, and an optional bit area (determined by the value of the second operation code part) of a source register is extracted and stored in an optional bit area of destination (a register of the general register file or the memory), thereby making it possible to "process the insertion and extraction operations to and from optional byte positions of registers" at a high speed with short instruction code size.

摘要翻译： 一种数据处理器，其具有对包括两个操作码部分的指令代码，源操作数指定部分和目的地操作数指定部分进行解码的微解码器，其中源数据的可选位区（通用寄存器文件或存储器的寄存器） 根据解码结果插入到目的地寄存器的可选位区域（由第一操作码部分的值确定）和源寄存器的可选位区域（由第二操作码部分的值确定） 被提取并存储在目的地的可选位区（通用寄存器文件或存储器的寄存器）中，从而使得可以以高速“处理到寄存器的可选字节位置的插入和提取操作”成为可能， 短指令代码大小。

公开(公告)号：US5524226A

公开(公告)日：1996-06-04

申请号：US434605

申请日：1995-05-03

申请人： Masaaki Arioka ,  Shigeo Mizugaki

发明人： Masaaki Arioka ,  Shigeo Mizugaki

IPC分类号： G06F9/30 ,  G06F12/06 ,  G06F15/78 ,  G11C7/00 ,  G11C11/401 ,  G11C11/407 ,  G06F12/02

CPC分类号： G11C7/00

摘要： To speed up data transfer of a plurality of registers between register banks in a microcomptuer having a register file formed by a built-in RAM and consisting of a plurality of register banks, the memory cells of the same type of registers belonging to different register banks are connected to the same bit lines. For data transfer of a plurality of registers between register banks, the word line 12 connecting a source register bank is first activated to output data to bit lines 13, and then the word line 12 connecting to a destination register bank is activated to read the data outputted to the bit lines 13, thus making it possible to speed up data transfer of a plurality of registers without the use of the internal data bus 3 of the microcomputer.

摘要翻译： 为了加速具有由内置RAM形成的由多个寄存器组组成的寄存器文件的微型计数器中的寄存器组之间的多个寄存器的数据传输，属于不同寄存器组的相同类型寄存器的存储单元 连接到相同的位线。 对于寄存器组之间的多个寄存器的数据传输，首先激活连接源寄存器组的字线12以将数据输出到位线13，然后激活连接到目的地寄存器组的字线12以读取数据 输出到位线13，从而使得可以在不使用微型计算机的内部数据总线3的情况下加速多个寄存器的数据传送。