利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

8 条记录 (耗时 0.018 秒)

    Programmable precharge circuitry
    2.
    发明授权
    Programmable precharge circuitry 有权
    可编程预充电电路

    公开(公告)号：US08619482B1

    公开(公告)日：2013-12-31

    申请号：US12702206

    申请日：2010-02-08

    申请人： John Henry Bui ,  Triet M. Nguyen

    发明人： John Henry Bui ,  Triet M. Nguyen

    IPC分类号： G11C7/00

    CPC分类号： G11C7/04 ,  G11C7/12 ,  G11C11/419

    摘要： Integrated circuits with memory circuitry are provided. The memory circuitry may include rows of data line segments. Each data line segment may have associated memory cells, a programmable-strength precharge circuit, a latch circuit, a programmable-strength pull-up circuit, and a data line segment buffer. The precharge circuit may include multiple paths that can be switched into use depending on the configuration of programmable bits. The programmable-strength pull-up circuit may include multiple pull-up paths. The number of pull-up paths in use can be configured. The latch circuit may include a latch inverter that enables the programmable latch circuit during precharge operations. During a precharge period, the latch circuit can be disabled to block contending pull-down current and the data line segment buffer can be disabled to avoid crossbar currents.

    摘要翻译： 提供了具有存储器电路的集成电路。 存储器电路可以包括行数据线段。 每个数据线段可以具有相关联的存储器单元，可编程强度预充电电路，锁存电路，可编程强度上拉电路和数据线段缓冲器。 预充电电路可以包括根据可编程位的配置可以切换使用的多个路径。 可编程强度上拉电路可以包括多个上拉路径。 可以配置使用中的上拉路径数量。 锁存电路可以包括锁存逆变器，其在预充电操作期间使能可编程锁存电路。 在预充电期间，锁存电路可以被禁止以阻止有争议的下拉电流，并且可以禁止数据线段缓冲器以避免交叉电流。

    Specialized processing block for programmable logic device
    3.
    发明授权
    Specialized processing block for programmable logic device 有权
    可编程逻辑器件专用处理块

    公开(公告)号：US08266198B2

    公开(公告)日：2012-09-11

    申请号：US11447329

    申请日：2006-06-05

    申请人： Kwan Yee Martin Lee ,  Martin Langhammer ,  Yi-Wen Lin ,  Triet M. Nguyen

    发明人： Kwan Yee Martin Lee ,  Martin Langhammer ,  Yi-Wen Lin ,  Triet M. Nguyen

    IPC分类号： G06F7/38 ,  H03K19/173 ,  H03K19/177

    CPC分类号： G06F7/49963 ,  G06F7/49921 ,  G06F7/49947 ,  G06F7/5443

    摘要： A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing block preferably also includes saturation circuitry to prevent overflows and underflows, and the bit position at which saturation occurs also preferably is selectable. The selectability of both the rounding and saturation positions provides control of the output data word width. The rounding and saturation circuitry may be selectably located in different positions based on timing needs. Similarly, rounding may be speeded up using a look-ahead mode in which both rounded and unrounded results are computed in parallel, with the rounding logic selecting between those results.

    摘要翻译： 用于可编程逻辑器件的专用处理块包括用于执行其乘法和和的电路，以及用于对结果进行舍入的电路。 四舍五入电路可以选择性地执行圆到最近和从最接近平移的操作。 此外，优选地可选择进行舍入的位位置。 专门的处理块优选地还包括用于防止溢出和下溢的饱和电路，并且优选地可选择饱和发生的位位置。 舍入和饱和位置的选择性提供了输出数据字宽度的控制。 舍入和饱和电路可以基于定时需要可选地位于不同的位置。 类似地，可以使用前瞻模式来加速舍入，其中舍入和未包围的结果被并行计算，舍入逻辑在这些结果之间进行选择。

    Memory elements with leakage compensation
    4.
    发明授权
    Memory elements with leakage compensation 有权
    具有泄漏补偿的存储元件

    公开(公告)号：US07864603B1

    公开(公告)日：2011-01-04

    申请号：US12037911

    申请日：2008-02-26

    申请人： John Henry Bui ,  Triet M. Nguyen ,  David E. Jefferson

    发明人： John Henry Bui ,  Triet M. Nguyen ,  David E. Jefferson

    IPC分类号： G11C7/18

    CPC分类号： G11C7/12 ,  G11C11/412 ,  G11C11/413

    摘要： Integrated circuits with memory elements are provided. The memory elements may be arranged in an array. Data lines may be used to load data into the memory elements and may be used to read data from the memory elements. The memory elements may be used to store configuration data on a programmable logic device integrated circuit. Each memory element may have an output that supplies a programmable transistor gate with a static control signal. Data reading circuitry may be coupled to each data line to read data from an addressed memory element on that data line. The data reading circuitry for each data line may include a precharge transistor and an output latch. The output latch may contain cross-coupled inverters. An inwardly-directed inverter in the output latch may have a pull-up transistor that is connected in series with a current source.

    摘要翻译： 提供具有存储元件的集成电路。 存储器元件可以排列成阵列。 数据线可以用于将数据加载到存储器元件中，并且可以用于从存储器元件读取数据。 存储器元件可用于将配置数据存储在可编程逻辑器件集成电路上。 每个存储元件可以具有向可编程晶体管栅极提供静态控制信号的输出。 数据读取电路可以耦合到每个数据线以从该数据线上的寻址的存储器元件读取数据。 每个数据线的数据读取电路可以包括预充电晶体管和输出锁存器。 输出锁存器可以包含交叉耦合的反相器。 输出锁存器中的向内指向的反相器可以具有与电流源串联连接的上拉晶体管。

    Reconfigurable logic block with user RAM
    6.
    发明授权
    Reconfigurable logic block with user RAM 有权
    用户RAM可重构逻辑块

    公开(公告)号：US08436646B1

    公开(公告)日：2013-05-07

    申请号：US13175662

    申请日：2011-07-01

    申请人： David W. Mendel ,  Triet M. Nguyen ,  Lu Zhou ,  Gary Lai

    发明人： David W. Mendel ,  Triet M. Nguyen ,  Lu Zhou ,  Gary Lai

    IPC分类号： H03K19/173

    CPC分类号： H03K19/17724

    摘要： A programmable logic device includes logic blocks such as a logic array blocks (LAB) that can be configured as a random access memory (RAM) or as a lookup table (LUT). A mode flag is provided to indicate the mode of operation of configuration logic such as a configuration RAM (CRAM) used during partial reconfiguration of a logic block. If the mode flag indicates a design state, the configuration logic associated with the logic block is included in data verification and correction processes. If the mode flag indicates a user defined state, the configuration logic associated with the logic block is excluded from data verification and correction processes. Thus, exclusion and inclusion of portions of a region of configuration logic from data verification and correction processes allow a region of configuration logic to store both a design state and a user defined state without causing deleterious effects.

    摘要翻译： 可编程逻辑器件包括诸如可被配置为随机存取存储器（RAM）或查找表（LUT）的逻辑阵列块（LAB）的逻辑块。 提供模式标志以指示诸如在逻辑块的部分重新配置期间使用的配置RAM（CRAM）的配置逻辑的操作模式。 如果模式标志指示设计状态，则与逻辑块相关联的配置逻辑被包括在数据验证和校正处理中。 如果模式标志指示用户定义的状态，则与逻辑块相关联的配置逻辑从数据验证和校正处理中排除。 因此，排除和包含来自数据验证和校正处理的配置逻辑区域的部分允许配置逻辑的区域既存储设计状态又限制用户定义的状态，而不会造成有害影响。

    Adder-rounder circuitry for specialized processing block in programmable logic device
    7.
    发明授权
    Adder-rounder circuitry for specialized processing block in programmable logic device 有权
    用于可编程逻辑器件中专用处理块的加法器电路

    公开(公告)号：US07822799B1

    公开(公告)日：2010-10-26

    申请号：US11426403

    申请日：2006-06-26

    申请人： Martin Langhammer ,  Triet M. Nguyen ,  Yi-Wen Lin

    发明人： Martin Langhammer ,  Triet M. Nguyen ,  Yi-Wen Lin

    IPC分类号： G06F7/38

    CPC分类号： G06F7/509 ,  G06F7/49963 ,  G06F7/5016 ,  G06F7/508

    摘要： Adder/rounder circuitry for use in a programmable logic device computes a rounded sum quickly, and ideally within one clock cycle. The rounding position is selectable within a range of bit positions. In an input stage, for each bit position in that range, bits from both addends and a rounding bit are processed, while for each bit position outside that range only bits from both addends are processed. The input stage processing aligns its output in a common format for bits within and outside the range. The input processing may include 3:2 compression for bit positions within the range and 2:2 compression for bit positions outside the range, so that further processing is performed for all bit positions on a sum vector and a carry vector. Computation of the sum proceeds substantially simultaneously with and without the rounding input, and rounding logic makes a selection later in the computation.

    摘要翻译： 用于可编程逻辑器件的加法器/圆形电路可以快速计算舍入的并且理想地在一个时钟周期内计算。 舍入位置可在位位置范围内选择。 在输入级中，对于该范围内的每个位位置，处理来自两个加数和舍入位的位，而对于该范围之外的每个位位置，只处理来自两个加数的位。 输入级处理以范围内和外的位的通用格式对齐其输出。 输入处理可以包括在该范围内的比特位置的3：2压缩，以及在该范围之外的比特位置的2：2压缩，使得对和矢量和进位向量的所有比特位置执行进一步的处理。 总和的计算基本上与舍入输入同时进行，并且舍入逻辑在计算中稍后进行选择。

    Specialized processing block for programmable logic device
    8.
    发明申请
    Specialized processing block for programmable logic device 有权
    可编程逻辑器件专用处理块

    公开(公告)号：US20070185951A1

    公开(公告)日：2007-08-09

    申请号：US11447329

    申请日：2006-06-05

    申请人： Kwan Yee Martin Lee ,  Martin Langhammer ,  Yi-Wen Lin ,  Triet M. Nguyen

    发明人： Kwan Yee Martin Lee ,  Martin Langhammer ,  Yi-Wen Lin ,  Triet M. Nguyen

    IPC分类号： G06F7/00

    CPC分类号： G06F7/49963 ,  G06F7/49921 ,  G06F7/49947 ,  G06F7/5443

    摘要： A specialized processing block for a programmable logic device includes circuitry for performing multiplications and sums thereof, as well as circuitry for rounding the result. The rounding circuitry can selectably perform round-to-nearest and round-to-nearest-even operations. In addition, the bit position at which rounding occurs is preferably selectable. The specialized processing block preferably also includes saturation circuitry to prevent overflows and underflows, and the bit position at which saturation occurs also preferably is selectable. The selectability of both the rounding and saturation positions provides control of the output data word width. The rounding and saturation circuitry may be selectably located in different positions based on timing needs. Similarly, rounding may be speeded up using a look-ahead mode in which both rounded and unrounded results are computed in parallel, with the rounding logic selecting between those results.

    摘要翻译： 用于可编程逻辑器件的专用处理块包括用于执行其乘法和和的电路，以及用于对结果进行舍入的电路。 四舍五入电路可以选择性地执行圆到最近和从最接近平移的操作。 此外，优选地可选择进行舍入的位位置。 专门的处理块优选地还包括用于防止溢出和下溢的饱和电路，并且优选地可选择饱和发生的位位置。 舍入和饱和位置的选择性提供了输出数据字宽度的控制。 舍入和饱和电路可以基于定时需要可选地位于不同的位置。 类似地，可以使用前瞻模式来加速舍入，其中舍入和未包围的结果被并行计算，舍入逻辑在这些结果之间进行选择。