利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

20 条记录 (耗时 0.031 秒)

    Memory elements with leakage compensation
    1.
    发明授权
    Memory elements with leakage compensation 有权
    具有泄漏补偿的存储元件

    公开(公告)号：US07864603B1

    公开(公告)日：2011-01-04

    申请号：US12037911

    申请日：2008-02-26

    申请人： John Henry Bui ,  Triet M. Nguyen ,  David E. Jefferson

    发明人： John Henry Bui ,  Triet M. Nguyen ,  David E. Jefferson

    IPC分类号： G11C7/18

    CPC分类号： G11C7/12 ,  G11C11/412 ,  G11C11/413

    摘要： Integrated circuits with memory elements are provided. The memory elements may be arranged in an array. Data lines may be used to load data into the memory elements and may be used to read data from the memory elements. The memory elements may be used to store configuration data on a programmable logic device integrated circuit. Each memory element may have an output that supplies a programmable transistor gate with a static control signal. Data reading circuitry may be coupled to each data line to read data from an addressed memory element on that data line. The data reading circuitry for each data line may include a precharge transistor and an output latch. The output latch may contain cross-coupled inverters. An inwardly-directed inverter in the output latch may have a pull-up transistor that is connected in series with a current source.

    摘要翻译： 提供具有存储元件的集成电路。 存储器元件可以排列成阵列。 数据线可以用于将数据加载到存储器元件中，并且可以用于从存储器元件读取数据。 存储器元件可用于将配置数据存储在可编程逻辑器件集成电路上。 每个存储元件可以具有向可编程晶体管栅极提供静态控制信号的输出。 数据读取电路可以耦合到每个数据线以从该数据线上的寻址的存储器元件读取数据。 每个数据线的数据读取电路可以包括预充电晶体管和输出锁存器。 输出锁存器可以包含交叉耦合的反相器。 输出锁存器中的向内指向的反相器可以具有与电流源串联连接的上拉晶体管。

    System for distributing clocks using a delay lock loop in a programmable logic circuit
    2.
    发明授权
    System for distributing clocks using a delay lock loop in a programmable logic circuit 失效
    用于在可编程逻辑电路中使用延迟锁定环路分配时钟的系统

    公开(公告)号：US5963069A

    公开(公告)日：1999-10-05

    申请号：US971315

    申请日：1997-11-17

    申请人： David E. Jefferson ,  L. Todd Cope ,  Srinivas Reddy ,  Richard G. Cliff

    发明人： David E. Jefferson ,  L. Todd Cope ,  Srinivas Reddy ,  Richard G. Cliff

    IPC分类号： G06F1/10 ,  H03K19/177 ,  H03L7/081 ,  H03L7/087 ,  H03L7/08

    CPC分类号： H03K19/1774 ,  G06F1/10 ,  H03K19/17732 ,  H03L7/0814 ,  H03L7/087

    摘要： A system (100) for distributing a clock signal to many points on an integrated circuit. The system includes using a delay lock loop with specific digital circuits to accomplish the phase error detection and delay element selection. In one embodiment, two flip-flops are used to detect a phase error. In another embodiment, both macro (202) and micro phase detectors (218) are used and the delay element selection is performed in two stages by using a shift register (210) in a first stage and a counter (220) in a second stage. Another feature of the present invention is, the ability to distribute the reference clock or a synchronized clock to different portions of the circuitry on an integrated circuit. Multiple clock distribution systems are provided which may be selected.

    摘要翻译： 一种用于将时钟信号分配给集成电路上的许多点的系统（100）。 该系统包括使用具有特定数字电路的延迟锁定环来完成相位误差检测和延迟元件选择。 在一个实施例中，使用两个触发器来检测相位误差。 在另一个实施例中，使用宏（202）和微相位检测器（218），并且通过使用第一级中的移位寄存器（210）和在第二级中的计数器（220），两级执行延迟元件选择 。 本发明的另一个特征是将参考时钟或同步时钟分配到集成电路上的电路的不同部分的能力。 提供可选择的多个时钟分配系统。

    Flexible RAM Clock Enable
    3.
    发明申请
    Flexible RAM Clock Enable 有权
    灵活的RAM时钟使能

    公开(公告)号：US20080253220A1

    公开(公告)日：2008-10-16

    申请号：US12145440

    申请日：2008-06-24

    申请人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

    发明人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

    IPC分类号： G11C8/18

    CPC分类号： G11C7/1075 ,  G11C8/18 ,  H03K19/1737

    摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block.

    摘要翻译： 第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。 第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。

    Programmable memory access parameters
    4.
    发明授权
    Programmable memory access parameters 有权
    可编程存储器访问参数

    公开(公告)号：US07236411B1

    公开(公告)日：2007-06-26

    申请号：US11187356

    申请日：2005-07-21

    申请人： Rahul Saini ,  Changsong Zhang ,  David E. Jefferson

    发明人： Rahul Saini ,  Changsong Zhang ,  David E. Jefferson

    IPC分类号： G11C7/00

    CPC分类号： G11C7/22 ,  G06F17/5054 ,  G11C7/222

    摘要： A programmable device can configure memory access parameters to optimize the performance of one or more of its memory units. A memory unit includes one or more programmable delay units connected with clock, control and/or data signals. The configuration data of the programmable device specifies delay values for each programmable delay unit. A programmable delay unit includes at least two signal paths having different timing characteristics. A switching circuit controlled by configuration data is used to select one of the signal paths as the output of the programmable delay unit. Programmable delay units can be connected in series or in parallel to increase the number of possible delays and/or to specify timing parameters of portions of the memory unit in absolute or relative terms. Programmable delay units can be used to vary the timing characteristics of the memory unit and to control the voltage split used to read data.

    摘要翻译： 可编程设备可以配置存储器访问参数以优化其一个或多个存储器单元的性能。 存储器单元包括与时钟，控制和/或数据信号连接的一个或多个可编程延迟单元。 可编程设备的配置数据指定每个可编程延迟单元的延迟值。 可编程延迟单元包括具有不同定时特性的至少两个信号路径。 由配置数据控制的开关电路用于选择一个信号路径作为可编程延迟单元的输出。 可编程延迟单元可以串联或并联连接以增加可能的延迟的数量和/或以绝对或相对的方式指定存储器单元的部分的定时参数。 可编程延迟单元可用于改变存储器单元的定时特性并控制用于读取数据的电压分配。

    Programmable logic with on-chip DLL or PLL to distribute clock
    5.
    发明授权
    Programmable logic with on-chip DLL or PLL to distribute clock 有权
    具有片内DLL或PLL的可编程逻辑来分配时钟

    公开(公告)号：US06292016B1

    公开(公告)日：2001-09-18

    申请号：US09588034

    申请日：2000-06-05

    申请人： David E. Jefferson ,  L. Todd Cope ,  Srinivas Reddy ,  Richard G. Cliff

    发明人： David E. Jefferson ,  L. Todd Cope ,  Srinivas Reddy ,  Richard G. Cliff

    IPC分类号： G03F738

    CPC分类号： H03K19/1774 ,  G06F1/10 ,  H03K19/17732 ,  H03L7/0814 ,  H03L7/087

    摘要： A programmable logic device or field programmable gate array includes an on-chip clock synchronization circuit to synchronize a reference or system clock signal. The clock synchronization circuit is a delay-locked loop (DLL) circuit in one implementation and a phase locked loop (PLL) circuit in another implementation. The DLL or PLL circuits may be analog or digital. The clock synchronization circuit generates a synchronized clock signal that is distributed throughout the programmable integrated circuit. The synchronized clock signal is programmably connected to the programmable logic elements or logic array blocks (LABs) of the integrated circuit. The clock synchronization circuit reduces or minimizes clock skew when distributing a clock signal within the integrated circuit. The clock synchronization circuit improves the overall performance of the programmable logic integrated circuit.

    摘要翻译： 可编程逻辑器件或现场可编程门阵列包括片上时钟同步电路以同步参考或系统时钟信号。 时钟同步电路是一个实现中的延迟锁定环（DLL）电路和另一个实现中的锁相环（PLL）电路。 DLL或PLL电路可以是模拟或数字的。 时钟同步电路产生分布在整个可编程集成电路中的同步时钟信号。 同步时钟信号可编程地连接到集成电路的可编程逻辑元件或逻辑阵列块（LAB）。 当在集成电路内分配时钟信号时，时钟同步电路减小或最小化时钟偏移。 时钟同步电路提高了可编程逻辑集成电路的整体性能。

    Programmable logic device memory cell circuit
    6.
    发明授权
    Programmable logic device memory cell circuit 有权
    可编程逻辑器件存储单元电路

    公开(公告)号：US6115312A

    公开(公告)日：2000-09-05

    申请号：US167637

    申请日：1998-10-06

    申请人： David E. Jefferson ,  Bruce B. Pedersen

    发明人： David E. Jefferson ,  Bruce B. Pedersen

    IPC分类号： G11C11/41 ,  G11C7/00 ,  G11C7/20 ,  G11C11/412 ,  G11C29/04

    CPC分类号： G11C11/412 ,  G11C7/20

    摘要： A memory cell circuit for a programmable logic device is provided that allows groups of memory cells to be powered down when one or more of the memory cells in a group is defective. Each memory cell contains two cross-coupled inverters for storing programming data for the programmable logic device. A first inverter in each cell is powered by a global power signal. A second inverter in each cell is powered by a power supply signal. The memory cells are powered down by taking the global power signal low while maintaining the power supply signal high. Because the second inverter remains active during power down, the memory cells may be shut down completely. The memory cell circuit may be used to set all of the memory cells to a known state upon power up.

    摘要翻译： 提供了一种用于可编程逻辑器件的存储单元电路，其中当组中的一个或多个存储器单元有缺陷时，允许存储单元组被断电。 每个存储单元包含两个交叉耦合的反相器，用于存储可编程逻辑器件的编程数据。 每个单元中的第一个反相器由全局功率信号供电。 每个单元中的第二个反相器由电源信号供电。 在保持电源信号为高电平的同时，将全局电源信号置于低电平，使存储单元断电。 由于第二个反相器在掉电期间保持有效，因此存储单元可能完全关闭。 存储单元电路可以用于在加电时将所有存储单元设置为已知状态。

    Flexible RAM clock enable
    7.
    发明授权
    Flexible RAM clock enable 失效
    灵活的RAM时钟使能

    公开(公告)号：US07397726B1

    公开(公告)日：2008-07-08

    申请号：US11399771

    申请日：2006-04-07

    申请人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

    发明人： Jinyong Yuan ,  Christopher F. Lane ,  David E. Jefferson ,  Vaughn Betz

    IPC分类号： G11C8/00 ,  G11C7/10

    CPC分类号： G11C7/1075 ,  G11C8/18 ,  H03K19/1737

    摘要： A first set of configuration logic is configurable to provide a first port input clock signal for controlling input registers of a first port of a memory block. The first set of configuration logic is also configurable to provide a first port core clock signal for controlling the memory block core. The first port core clock signal can either be the same as the first port input clock signal, or can be controlled independently from the first port input clock signal. A second set of configuration logic is configurable to provide a second port input clock signal for controlling input registers of a second port of the memory block. The second set of configuration logic is also configurable to provide a second port core clock signal for controlling the memory block core. The second port core clock signal can be controlled independently from the second port input clock signal.

    摘要翻译： 第一组配置逻辑可配置为提供用于控制存储器块的第一端口的输入寄存器的第一端口输入时钟信号。 第一组配置逻辑也可配置为提供用于控制存储块核心的第一端口核心时钟信号。 第一个端口核心时钟信号可以与第一个端口输入时钟信号相同，也可以独立于第一个端口输入时钟信号进行控制。 第二组配置逻辑可配置为提供用于控制存储器块的第二端口的输入寄存器的第二端口输入时钟信号。 第二组配置逻辑也可配置为提供用于控制存储块核心的第二端口核心时钟信号。 可以独立于第二端口输入时钟信号来控制第二端口核心时钟信号。

    Redundancy circuitry for programmable logic devices with interleaved input circuits
    10.
    发明授权
    Redundancy circuitry for programmable logic devices with interleaved input circuits 失效

    公开(公告)号：US6107820A

    公开(公告)日：2000-08-22

    申请号：US82081

    申请日：1998-05-20

    申请人： David E. Jefferson ,  Srinivas T. Reddy

    发明人： David E. Jefferson ,  Srinivas T. Reddy

    IPC分类号： H03K19/173 ,  G06F11/20 ,  G06F7/38

    CPC分类号： H03K19/17764 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/1778

    摘要： Redundant circuitry is provided for a programmable logic device that uses an interleaved input multiplexer circuit arrangement. The programmable logic device has at least one row of logic regions and has multiple columns, each of which contains one of the interleaved input multiplexers and one of the logic regions. A set of conductors associated with the row of logic regions is used to convey signals between the logic regions. Each interleaved logic region distributes logic signals from the conductors in the row to two adjacent logic regions. Bypass circuitry is provided in each column for bypassing the interleaved input multiplexer and logic region in that column. If a defect is detected in a column during testing of the device, the manufacturer can repair the device using the bypass circuitry to bypass that column. Spare logic is provided to replace the circuitry lost when a defective column is bypassed.