公开(公告)号：US07864603B1

公开(公告)日：2011-01-04

申请号：US12037911

申请日：2008-02-26

申请人： John Henry Bui ,  Triet M. Nguyen ,  David E. Jefferson

发明人： John Henry Bui ,  Triet M. Nguyen ,  David E. Jefferson

IPC分类号： G11C7/18

CPC分类号： G11C7/12 ,  G11C11/412 ,  G11C11/413

摘要： Integrated circuits with memory elements are provided. The memory elements may be arranged in an array. Data lines may be used to load data into the memory elements and may be used to read data from the memory elements. The memory elements may be used to store configuration data on a programmable logic device integrated circuit. Each memory element may have an output that supplies a programmable transistor gate with a static control signal. Data reading circuitry may be coupled to each data line to read data from an addressed memory element on that data line. The data reading circuitry for each data line may include a precharge transistor and an output latch. The output latch may contain cross-coupled inverters. An inwardly-directed inverter in the output latch may have a pull-up transistor that is connected in series with a current source.

摘要翻译： 提供具有存储元件的集成电路。 存储器元件可以排列成阵列。 数据线可以用于将数据加载到存储器元件中，并且可以用于从存储器元件读取数据。 存储器元件可用于将配置数据存储在可编程逻辑器件集成电路上。 每个存储元件可以具有向可编程晶体管栅极提供静态控制信号的输出。 数据读取电路可以耦合到每个数据线以从该数据线上的寻址的存储器元件读取数据。 每个数据线的数据读取电路可以包括预充电晶体管和输出锁存器。 输出锁存器可以包含交叉耦合的反相器。 输出锁存器中的向内指向的反相器可以具有与电流源串联连接的上拉晶体管。

公开(公告)号：US08619482B1

公开(公告)日：2013-12-31

申请号：US12702206

申请日：2010-02-08

申请人： John Henry Bui ,  Triet M. Nguyen

发明人： John Henry Bui ,  Triet M. Nguyen

IPC分类号： G11C7/00

CPC分类号： G11C7/04 ,  G11C7/12 ,  G11C11/419

摘要： Integrated circuits with memory circuitry are provided. The memory circuitry may include rows of data line segments. Each data line segment may have associated memory cells, a programmable-strength precharge circuit, a latch circuit, a programmable-strength pull-up circuit, and a data line segment buffer. The precharge circuit may include multiple paths that can be switched into use depending on the configuration of programmable bits. The programmable-strength pull-up circuit may include multiple pull-up paths. The number of pull-up paths in use can be configured. The latch circuit may include a latch inverter that enables the programmable latch circuit during precharge operations. During a precharge period, the latch circuit can be disabled to block contending pull-down current and the data line segment buffer can be disabled to avoid crossbar currents.

摘要翻译： 提供了具有存储器电路的集成电路。 存储器电路可以包括行数据线段。 每个数据线段可以具有相关联的存储器单元，可编程强度预充电电路，锁存电路，可编程强度上拉电路和数据线段缓冲器。 预充电电路可以包括根据可编程位的配置可以切换使用的多个路径。 可编程强度上拉电路可以包括多个上拉路径。 可以配置使用中的上拉路径数量。 锁存电路可以包括锁存逆变器，其在预充电操作期间使能可编程锁存电路。 在预充电期间，锁存电路可以被禁止以阻止有争议的下拉电流，并且可以禁止数据线段缓冲器以避免交叉电流。

公开(公告)号：US08476947B2

公开(公告)日：2013-07-02

申请号：US13295875

申请日：2011-11-14

申请人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

发明人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K19/018592 ,  H03K19/09429

摘要： Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

公开(公告)号：US08384460B1

公开(公告)日：2013-02-26

申请号：US13420349

申请日：2012-03-14

申请人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

发明人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

IPC分类号： H03H11/16

CPC分类号： H03L7/0814 ,  H03K2005/00293

摘要： An adjustable delay circuit includes first and second transistors each having a control input coupled to an input node of the adjustable delay circuit and an output coupled to an output node of the adjustable delay circuit. The adjustable delay circuit includes a first pass gate coupled between first and second capacitors and the output node of the adjustable delay circuit. The first and the second capacitors are coupled between a node at a high voltage and a node at a low voltage. The first pass gate is operable to be controlled by a first delay control signal.

摘要翻译： 可调延迟电路包括第一和第二晶体管，每个晶体管具有耦合到可调延迟电路的输入节点的控制输入和耦合到可调延迟电路的输出节点的输出。 可调延迟电路包括耦合在第一和第二电容器之间的第一通过栅极和可调延迟电路的输出节点。 第一和第二电容器耦合在高电压节点和低电压节点之间。 第一通过门可操作以由第一延迟控制信号控制。

公开(公告)号：US08149038B1

公开(公告)日：2012-04-03

申请号：US12729114

申请日：2010-03-22

申请人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

发明人： Chiakang Sung ,  John Henry Bui ,  Khai Nguyen ,  Bonnie I. Wang ,  Xiaobao Wang

IPC分类号： H03H11/16

CPC分类号： H03L7/0814 ,  H03K2005/00293

摘要： A dynamic phase alignment circuit includes a phase generator circuit having delay-locked loop circuits that generate periodic output signals. Each of the delay-locked loop circuits generates one of the periodic output signals in response to at least two periodic input signals. A multiplexer circuit selects a selected periodic signal from among the periodic input signals and the periodic output signals based on select signals. A phase detection circuit compares a phase of the selected periodic signal to a data signal to generate a phase detection signal. A control logic circuit generates the select signals. The control logic circuit adjusts the select signals based on changes in the phase detection signal to cause the multiplexer circuit to adjust the phase of the selected periodic signal.

摘要翻译： 动态相位对准电路包括具有产生周期性输出信号的延迟锁定环路电路的相位发生器电路。 每个延迟锁定环路电路响应于至少两个周期性输入信号产生周期性输出信号之一。 多路复用器电路基于选择信号从周期性输入信号和周期性输出信号中选择选定的周期信号。 相位检测电路将选择的周期信号的相位与数据信号进行比较，以产生相位检测信号。 控制逻辑电路产生选择信号。 控制逻辑电路基于相位检测信号的变化来调整选择信号，以使多路复用器电路调整所选周期信号的相位。

公开(公告)号：US07973553B1

公开(公告)日：2011-07-05

申请号：US12721759

申请日：2010-03-11

申请人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  John Henry Bui

发明人： Xiaobao Wang ,  Chiakang Sung ,  Bonnie I. Wang ,  Khai Nguyen ,  John Henry Bui

IPC分类号： H03K17/16 ,  H03K19/003

CPC分类号： H04L25/0278

摘要： A circuit includes first transistors and a comparator. The comparator compares a reference signal and a signal that is based on conductive states of the first transistors. A control circuit generates first control signals based on an output signal of the comparator. The conductive states of the first transistors are determined based on the first control signals. An arithmetic circuit performs an arithmetic function based on the first control signals and second control signals to generate calibration signals. Second transistors provide a termination impedance at an external terminal of the circuit that is based on the calibration signals.

摘要翻译： 电路包括第一晶体管和比较器。 比较器比较参考信号和基于第一晶体管的导电状态的信号。 控制电路根据比较器的输出信号产生第一控制信号。 基于第一控制信号来确定第一晶体管的导通状态。 算术电路基于第一控制信号和第二控制信号执行运算功能，以生成校准信号。 第二晶体管在基于校准信号的电路的外部端子处提供终端阻抗。

公开(公告)号：US06597199B1

公开(公告)日：2003-07-22

申请号：US09205257

申请日：1998-12-02

申请人： John Henry Bui

发明人： John Henry Bui

IPC分类号： H03K190175

CPC分类号： H03K17/164

摘要： An output buffer having one or more of the following advantages: (1) faster slew rate, (2) reduced switching noise during signal transitions, and (3) improved switching time. The output buffer includes a pair of output transistors. At least one of the output transistors is designed with dynamically adjustable beta that allows for robust control of the output buffer operating characteristics. The beta can be adjusted by changing the size of the output transistor. Transistor size can be changed, in turn, by enabling and disabling additional output transistor(s).

摘要翻译： 具有以下一个或多个优点的输出缓冲器：（1）更快的转换速率，（2）在信号转换期间降低的开关噪声，以及（3）改进的开关时间。 输出缓冲器包括一对输出晶体管。 至少有一个输出晶体管被设计成具有动态可调节的beta，允许对输出缓冲器工作特性的鲁棒控制。 可以通过改变输出晶体管的尺寸来调整beta。 晶体管尺寸可以通过启用和禁用附加的输出晶体管来进行更改。

公开(公告)号：US6122212A

公开(公告)日：2000-09-19

申请号：US71669

申请日：1998-05-01

申请人： John Henry Bui ,  Chien-fan Wang

发明人： John Henry Bui ,  Chien-fan Wang

IPC分类号： G11C7/02 ,  G11C7/06

CPC分类号： G11C7/062

摘要： A sense amplifier for detecting a logic state of a memory cell includes a voltage amplifier, a current mirror, and a feedback circuit. The voltage amplifier couples to the memory cell and the current mirror. The feedback circuit couples to the current mirror and an input of the sense amplifier. The feedback circuit can be implemented with a transistor, a switch, a transmission gate, or the like. The feedback circuit is selectively enabled to quickly charge or discharge the voltage at the input of the sense amplifier to a trip voltage of the sense amplifier. Whether charging or discharging is performed is dependent on the voltage then existing at the input node. The amount of charging and discharging current can also be based on other circuit considerations, such as the required charge time, and so on. When the voltage at the input reaches a predetermined voltage range, the feedback circuit is disabled.

摘要翻译： 用于检测存储单元的逻辑状态的读出放大器包括电压放大器，电流镜和反馈电路。 电压放大器耦合到存储单元和电流镜。 反馈电路耦合到电流镜和读出放大器的输入端。 反馈电路可以用晶体管，开关，传输门等来实现。 选择性地使反馈电路能够快速地将感测放大器的输入端的电压充电或放电到读出放大器的跳闸电压。 是否执行充电或放电取决于输入节点处存在的电压。 充电和放电电流的量也可以基于其他电路考虑，例如所需的充电时间等等。 当输入电压达到预定的电压范围时，反馈电路被禁止。

公开(公告)号：US20130120044A1

公开(公告)日：2013-05-16

申请号：US13295875

申请日：2011-11-14

申请人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

发明人： John Henry Bui ,  Lay Hock Khoo ,  Khai Nguyen ,  Chiakang Sung ,  Ket Chiew Sia

IPC分类号： H03K3/017

CPC分类号： H03K5/1565 ,  H03K19/018592 ,  H03K19/09429

摘要： Integrated circuits with clock generation and distribution circuitry are provided. Integrated circuits may include phase-locked loops configured to generate multiple clock signals that are delayed versions of one another. The clocks signal may be distributed to various regions on an integrated circuit using serially connected clock buffer blocks. Each buffer block may include bidirectional pairs of buffer circuits coupled in parallel. Each buffer circuit may have a first input configured to receive an input clock signal, an output at which a corrected version of the input clock signal is provided (e.g., an output at which an output clock signal with desired duty cycle is provided), a second input that receives a first delayed clock signal for setting the desired duty cycle for the output clock signal, and a third input that receives a second delayed clock signal that is high at least when the first delayed clock signal rises high.

摘要翻译： 提供了具有时钟发生和分配电路的集成电路。 集成电路可以包括被配置为生成作为彼此的延迟版本的多个时钟信号的锁相环。 时钟信号可以使用串行连接的时钟缓冲器块分布到集成电路上的各个区域。 每个缓冲块可以包括并联耦合的双向缓冲电路对。 每个缓冲电路可以具有被配置为接收输入时钟信号的第一输入，提供输入时钟信号的校正版本的输出（例如，提供具有期望的占空比的输出时钟信号的输出）， 第二输入端，接收用于设定所述输出时钟信号的期望占空比的第一延迟时钟信号;以及第三输入端，其接收至少当所述第一延迟时钟信号上升时为高的第二延迟时钟信号。

公开(公告)号：US06836144B1

公开(公告)日：2004-12-28

申请号：US10206250

申请日：2002-07-26

申请人： John Henry Bui ,  John Costello ,  Stephanie Tran

发明人： John Henry Bui ,  John Costello ,  Stephanie Tran

IPC分类号： H03K512

CPC分类号： H03K19/00384 ,  H04L25/0278

摘要： Circuits may provide series on-chip termination impedance to one or more input/output pins. In one embodiment, two off-chip reference resistors in combination with internal calibration circuitry are used to control termination transistors coupled to several input/output (I/O) pins. The termination transistors behave as programmably adjustable termination resistors that match the impedance of external resistors. By using only a small number of reference resistors (e.g., 2 resistors) for a large number of I/O pins, the present invention eliminates the external components that would otherwise be needed to provide resistance termination. The effective series termination resistance may be programmed, enabling the termination resistance to meet different I/O standards. Further, the resistance termination techniques of the present invention are not sensitive to process, voltage supply, and temperature (PVT) variations.

摘要翻译： 电路可以向一个或多个输入/输出引脚提供串联片上终止阻抗。 在一个实施例中，两个片外参考电阻器与内部校准电路组合用于控制耦合到多个输入/输出（I / O）引脚的端接晶体管。 端接晶体管表现为与外部电阻的阻抗匹配的可编程可调终端电阻。 通过仅使用少量的用于大量I / O引脚的参考电阻（例如，2个电阻），本发明消除了否则将需要提供电阻终止的外部组件。 可编程有效串联端接电阻，使终端电阻能够满足不同的I / O标准。 此外，本发明的电阻终止技术对于工艺，电压供应和温度（PVT）变化不敏感。