公开(公告)号：US08237479B2

公开(公告)日：2012-08-07

申请号：US12980359

申请日：2010-12-29

申请人： Hong-Sing Kao ,  Meng-Ta Yang ,  Tse-Hsiang Hsu

发明人： Hong-Sing Kao ,  Meng-Ta Yang ,  Tse-Hsiang Hsu

IPC分类号： H03L7/00

CPC分类号： H03L7/183 ,  H03K5/133 ,  H03K21/023 ,  H03K2005/00058 ,  H03K2005/00234

摘要： A delay line calibration mechanism includes a first delay line, a second delay line, a phase detector, and a controller. The first delay line receives a first pulse and a first delay selection signal, and delays the first pulse for a first delay period according to the first delay selection signal to output a first delayed pulse. The second delay line receives a second pulse and a second delay selection signal, and delays the second pulse for a second delay period according to the second delay selection signal to output a second delayed pulse. The phase detector generates a phase difference signal indicating the phase difference between the first delayed pulse and the second delayed pulse by comparing the first delayed pulse and the second delayed pulse. The controller generates the second delay selection signal, and generates the first delay selection signal according to the phase difference signal.

摘要翻译： 延迟线校准机构包括第一延迟线，第二延迟线，相位检测器和控制器。 第一延迟线接收第一脉冲和第一延迟选择信号，并且根据第一延迟选择信号将第一脉冲延迟第一延迟周期以输出第一延迟脉冲。 第二延迟线接收第二脉冲和第二延迟选择信号，并根据第二延迟选择信号将第二脉冲延迟第二延迟周期以输出第二延迟脉冲。 相位检测器通过比较第一延迟脉冲和第二延迟脉冲来产生指示第一延迟脉冲和第二延迟脉冲之间的相位差的相位差信号。 控制器产生第二延迟选择信号，并根据相位差信号产生第一延迟选择信号。

公开(公告)号：US20090296869A1

公开(公告)日：2009-12-03

申请号：US12407226

申请日：2009-03-19

申请人： Kuan-Hua Chao ,  Shiue-Shin Liu ,  Jeng-Horng Tsai ,  Chih-Ching Chen ,  Chuan Liu ,  Tse-Hsiang Hsu

发明人： Kuan-Hua Chao ,  Shiue-Shin Liu ,  Jeng-Horng Tsai ,  Chih-Ching Chen ,  Chuan Liu ,  Tse-Hsiang Hsu

IPC分类号： H04L7/00 ,  H03L7/06

CPC分类号： H03L7/081 ,  H03L7/087 ,  H03L7/1974

摘要： A clock generation circuit is provided and includes a phase locked loop (PLL) and a calibrator. The PLL is arranged to receive a first clock signal and generate the output clock signal. The PLL adjusts the frequency of the output clock signal according to a control signal. The calibrator is arranged to receive the output clock signal and a second clock signal, execute a frequency calibration between the output clock signal and the second clock signal, and generate the control signal according to results of the frequency calibration.

摘要翻译： 提供时钟发生电路并且包括锁相环（PLL）和校准器。 PLL被布置成接收第一时钟信号并产生输出时钟信号。 PLL根据控制信号调节输出时钟信号的频率。 校准器被布置成接收输出时钟信号和第二时钟信号，在输出时钟信号和第二时钟信号之间执行频率校准，并根据频率校准的结果产生控制信号。

公开(公告)号：US20090278574A1

公开(公告)日：2009-11-12

申请号：US12437541

申请日：2009-05-07

申请人： Hong-Sing Kao ,  Meng-Ta Yang ,  Kuan-Hua Chao ,  Tse-Hsiang Hsu

发明人： Hong-Sing Kao ,  Meng-Ta Yang ,  Kuan-Hua Chao ,  Tse-Hsiang Hsu

IPC分类号： H03K23/00 ,  H03L7/06

CPC分类号： H03L7/183 ,  H03K5/133 ,  H03K21/023 ,  H03K2005/00058 ,  H03K2005/00234

摘要： A frequency divider reduces jitter and power consumption, and includes a phase selector for receiving a plurality of clock signals and outputting an intermediate signal corresponding to phase characteristic of at least one of the clock signals, and an adjustable delay circuit for receiving the intermediate signal and generating an output signal by delaying the received intermediate signal.

摘要翻译： 分频器减少抖动和功耗，并且包括用于接收多个时钟信号并输出​​对应于至少一个时钟信号的相位特性的中间信号的相位选择器和用于接收中间信号的可调延迟电路，以及 通过延迟所接收的中间信号来产生输出信号。

公开(公告)号：US07471599B2

公开(公告)日：2008-12-30

申请号：US10880533

申请日：2004-07-01

申请人： Tse-Hsiang Hsu ,  Chih-Cheng Chen ,  Yuan-Chin Liu

发明人： Tse-Hsiang Hsu ,  Chih-Cheng Chen ,  Yuan-Chin Liu

IPC分类号： G11B7/0045

CPC分类号： G11B7/00456 ,  G11B7/1267

摘要： A write signal control circuit in an optical disk drive for adjusting the duty cycle of the write signals by a duty cycle adjusting unit. The write signal control circuit includes a write signal generator for converting an EFM signal into the write signals according to the write strategy waveform generating rules, a duty cycle adjusting unit for adjusting the duty cycle of each write signal according to adjusting parameters and for outputting adjusted write signals, and a duty cycle detector for detecting the duty cycle of each adjusted write signal and outputting a respective duty cycle control signal. The duty cycle adjusting unit further receives the duty cycle control signal to adapt the adjusting parameters.

摘要翻译： 一种光盘驱动器中的写入信号控制电路，用于通过占空比调节单元来调整写入信号的占空比。 写入信号控制电路包括写入信号发生器，用于根据写入策略波形生成规则将EFM信号转换成写入信号;占空比调整单元，用于根据调整参数调整每个写入信号的占空比， 写入信号，以及占空比检测器，用于检测每个经调整的写信号的占空比并输出相应的占空比控制信号。 占空比调整单元还接收占空比控制信号以适应调整参数。

公开(公告)号：US20070165511A1

公开(公告)日：2007-07-19

申请号：US11331206

申请日：2006-01-13

申请人： Tse-Hsiang Hsu ,  Chia-Hua Chou

发明人： Tse-Hsiang Hsu ,  Chia-Hua Chou

IPC分类号： G11B7/00

CPC分类号： G11B20/10009 ,  G11B7/09 ,  G11B7/12

摘要： A signal processing method and an optical pickup are capable of reducing signal distortion. Before being transmitted over a flexible cable to an optical disk drive controller, a low-pass filtering process is performed over the light detection signals or their arithmetic results in the optical pickup to eliminate high frequency compositions of the signals. By this way, the interference resulting from the flexible cable during signal transmission is mitigated. The retained data in the signals are further applied to recover servo control signals. Therefore, the stability of an optical disk servo control is improved, especially for a high-speed optical disk system.

摘要翻译： 信号处理方法和光学拾取器能够减少信号失真。 在通过柔性电缆传输到光盘驱动器控制器之前，对光拾取器中的光检测信号或其算术结果执行低通滤波处理以消除信号的高频组成。 通过这种方式，在信号传输期间由柔性电缆产生的干扰得到缓解。 信号中保留的数据进一步用于恢复伺服控制信号。 因此，提高了光盘伺服控制的稳定性，特别是对于高速光盘系统。

公开(公告)号：US20070052452A1

公开(公告)日：2007-03-08

申请号：US11456981

申请日：2006-07-12

申请人： Chia-Hua Chou ,  Tse-Hsiang Hsu

发明人： Chia-Hua Chou ,  Tse-Hsiang Hsu

IPC分类号： G11C27/02

CPC分类号： G11C5/145 ,  G11C27/024

摘要： A sample/hold circuit module. The sample/hold circuit module comprises a sample/hold circuit, an S/H controller, a pass transistor, and a high voltage generator. The sample/hold circuit comprises a capacitor and a sampling switch. The capacitor has a first electrode coupled to a first fixed voltage and a second electrode coupled to an output node of the sample/hold circuit module. The sampling switch comprises an output terminal coupled to the second electrode of the capacitor, an input terminal, and a control terminal. The S/H controller is coupled between the control terminal of the sampling switch and a second fixed voltage. The pass transistor has a sampling input terminal, an output terminal coupled to the input terminal of the sampling switch, and a control terminal. The high voltage generator is coupled between the control terminal of the pass transistor and the second fixed voltage.

摘要翻译： 采样/保持电路模块。 采样/保持电路模块包括采样/保持电路，S / H控制器，传输晶体管和高压发生器。 采样/保持电路包括电容器和采样开关。 电容器具有耦合到第一固定电压的第一电极和耦合到采样/保持电路模块的输出节点的第二电极。 采样开关包括耦合到电容器的第二电极的输出端子，输入端子和控制端子。 S / H控制器耦合在采样开关的控制端和第二固定电压之间。 传输晶体管具有采样输入端子，耦合到采样开关的输入端子的输出端子和控制端子。 高电压发生器耦合在传输晶体管的控制端和第二固定电压之间。

公开(公告)号：US07161417B2

公开(公告)日：2007-01-09

申请号：US11034739

申请日：2005-01-14

申请人： Tse-Hsiang Hsu ,  Chih-Cheng Chen

发明人： Tse-Hsiang Hsu ,  Chih-Cheng Chen

IPC分类号： H03K5/00

CPC分类号： H03L7/093

摘要： A loop filter and a method for adjusting its compensating current to make a control voltage of the loop filter more stable. The loop filter includes a charge/discharge path for receiving a control current and constituted by a first resister and a capacitor, a second resistor connected to the first terminal of the first resistor, an OP amplifier having an output terminal connected to the second resistor, a first input terminal connected to the capacitor, and a second input terminal, and a compensating unit connected to the output and second terminals of the second resistor. The loop filter further comprises a current source to provide a compensating current to the compensating unit. The loop filter utilizes the compensating unit to compensate the offset between the two input terminals of the amplifier. Therefore, the loop current of the OP amplifier can be reduced or eliminated.

摘要翻译： 一种环路滤波器和一种用于调整其补偿电流以使环路滤波器的控制电压更稳定的方法。 环路滤波器包括用于接收控制电流并由第一电阻器和电容器构成的充电/放电路径，连接到第一电阻器的第一端子的第二电阻器，具有连接到第二电阻器的输出端子的OP放大器， 连接到电容器的第一输入端子和第二输入端子，以及连接到第二电阻器的输出端子和第二端子的补偿单元。 环路滤波器还包括电流源以向补偿单元提供补偿电流。 环路滤波器利用补偿单元来补偿放大器的两个输入端之间的偏移。 因此，可以减少或消除OP放大器的回路电流。

公开(公告)号：US20050099215A1

公开(公告)日：2005-05-12

申请号：US11010420

申请日：2004-12-14

申请人： Tse-Hsiang Hsu ,  Chih-Cheng Chen

发明人： Tse-Hsiang Hsu ,  Chih-Cheng Chen

IPC分类号： H03L7/089 ,  H03L7/18 ,  H03L7/00

CPC分类号： H03L7/0895 ,  H03L7/18

摘要： A signal calibration apparatus of a charge pump minimizes a current from the charge pump. The signal calibration apparatus includes a detecting circuit, a current adjusting circuit, and a calibrating circuit, wherein the detecting circuit is coupled to the charge pump for outputting a detecting signal according to the direction and magnitude of the current, the current adjusting circuit is coupled to the detecting circuit for outputting a calibrating signal according to the polarity and magnitude of the slew rate of the detecting signal; and the calibrating circuit, which consists of a first calibration current source and a second calibration current source, is respectively coupled to the charge pump and the current adjusting circuit for adjusting the first current and the second current by outputting a first calibrating current and second calibrating current to the charge pump.

摘要翻译： 电荷泵的信号校准装置使来自电荷泵的电流最小化。 信号校准装置包括检测电路，电流调节电路和校准电路，其中检测电路耦合到电荷泵，用于根据电流的方向和幅度输出检测信号，电流调节电路耦合 检测电路，用于根据检测信号的转换速率的极性和大小输出校准信号; 并且由第一校准电流源和第二校准电流源组成的校准电路分别耦合到电荷泵和电流调节电路，用于通过输出第一校准电流和第二校准电流来调节第一电流和第二电流 电流到电荷泵。

公开(公告)号：US20050041565A1

公开(公告)日：2005-02-24

申请号：US10921806

申请日：2004-08-20

申请人： Tse-Hsiang Hsu ,  Chih-Cheng Chen

发明人： Tse-Hsiang Hsu ,  Chih-Cheng Chen

IPC分类号： G11B5/09 ,  G11B7/00 ,  G11B7/005 ,  G11B7/09

CPC分类号： G11B7/0053 ,  G11B7/0943

摘要： A control circuit for an optical pickup head in an optical disk drive for outputting filtered signals. The control circuit includes a laser drive unit for receiving a laser control signal to control a laser light source to generate a laser beam with a specified power, a photo detector for receiving the laser beam reflected from an optical disk and outputting a plurality of light detection signals, and a filter unit for filtering out the high frequency components of the light detection signals and then outputs the filtered signals. Since the high frequency components have been suppressed in the filtered signals, the transmission distortion can be reduced when the filtered signals are transmitted to the optical disk drive controller through a flexible cable. Accordingly, a more stable wobble signal can be obtained by the optical disk drive controller to enhance the stability of the optical disk drive operation based on the filtered signals.

摘要翻译： 一种用于输出滤波信号的用于光盘驱动器中的光学头的控制电路。 控制电路包括激光驱动单元，用于接收激光控制信号以控制激光源产生具有指定功率的激光束;光检测器，用于接收从光盘反射的激光束并输出多个光检测 信号和滤波器单元，用于滤除光检测信号的高频分量，然后输出滤波信号。 由于滤波信号中已经抑制了高频分量，所以当经过滤波的信号通过柔性电缆传输到光盘驱动器控制器时，可以减小传输失真。 因此，可以通过光盘驱动器控制器获得更稳定的摆动信号，以增强基于滤波信号的光盘驱动器操作的稳定性。

公开(公告)号：US06815987B2

公开(公告)日：2004-11-09

申请号：US10279102

申请日：2002-10-24

申请人： Tse-Hsiang Hsu ,  Chih-Cheng Chen

发明人： Tse-Hsiang Hsu ,  Chih-Cheng Chen

IPC分类号： H03L706

CPC分类号： H03L7/081 ,  H03L7/0891 ,  H04L7/0337

摘要： A phase locked loop (PLL), which has high operation speed and high resolution, and is particularly applicable in high frequency process, is disclosed. The PLL, receiving a data signal and generating a clock signal, comprises a voltage controlled oscillator (VCO) and multi-phase generator (MPG), a transition detector, an optimal phase encoder, and a phase selector, wherein the four devices are respectively used for outputting N phase clock signals of same frequency but different phases, for outputting a data period value and a clock period value by receiving the N phase clock signals, the data signal and the clock signal, for outputting a phase select signal according to the data period value and the clock period value, and for outputting one of the phase clock signals according to the phase select signal.