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    Driving circuit with load calibration and the method thereof
    3.
    发明授权
    Driving circuit with load calibration and the method thereof 有权
    带负载校准的驱动电路及其方法

    公开(公告)号：US07932740B1

    公开(公告)日：2011-04-26

    申请号：US12187361

    申请日：2008-08-06

    申请人： Kuan-Hua Chao ,  Jeng-Horng Tsai ,  Tse-Hsiang Hsu

    发明人： Kuan-Hua Chao ,  Jeng-Horng Tsai ,  Tse-Hsiang Hsu

    IPC分类号： H03K19/003

    CPC分类号： H03K19/0005 ,  H04L25/028

    摘要： A driving circuit includes: a first reference current source injects a reference current; each first switch unit is coupled between the first reference current source and one of first and second output ports; a second reference current source sinks the reference current; each second switch unit is coupled between the second reference current source and one of the output ports; a load unit is coupled between the output ports, and a common voltage is applied onto the load unit; and a calibration module calibrates an impedance of the load unit according to a voltage at one of the output ports, and the voltage is generated due to the reference current passing through one of the first switch units, the load unit, and one of the second switch units.

    摘要翻译： 驱动电路包括：第一参考电流源注入参考电流; 每个第一开关单元耦合在第一参考电流源和第一和第二输出端口之一之间; 第二参考电流源吸收参考电流; 每个第二开关单元耦合在第二参考电流源和其中一个输出端口之间; 负载单元耦合在输出端口之间，并且公共电压施加到负载单元上; 并且校准模块根据一个输出端口处的电压校准负载单元的阻抗，并且由于参考电流通过第一开关单元，负载单元中的一个和第二开关单元之一而产生电压 开关单元。

    Communication systems and clock generation circuits thereof with reference source switching
    4.
    发明授权
    Communication systems and clock generation circuits thereof with reference source switching 有权
    具有参考源切换的通信系统及其时钟发生电路

    公开(公告)号：US08526559B2

    公开(公告)日：2013-09-03

    申请号：US12410502

    申请日：2009-03-25

    申请人： Kuan-Hua Chao ,  Shiue-Shin Liu ,  Tse-Hsiang Hsu

    发明人： Kuan-Hua Chao ,  Shiue-Shin Liu ,  Tse-Hsiang Hsu

    IPC分类号： H03D3/24

    CPC分类号： H04L7/0091 ,  H04B15/02 ,  H04B2215/067 ,  H04L7/0083

    摘要： A clock generation circuit for a transmitter which transmits data according to an output clock signal is provided. The clock generation circuit include a clock generator and a phase locked loop (PLL). The clock generator generates a first clock signal. The PLL initially generates the output clock signal according to the first clock signal. When a frequency of the output clock signal generated according to the first clock signal is not within a range required for specification of the transmitter, the PLL generates the output clock signal according to a second clock signal.

    摘要翻译： 提供了一种用于根据输出时钟信号发送数据的发送器的时钟发生电路。 时钟发生电路包括时钟发生器和锁相环（PLL）。 时钟发生器产生第一个时钟信号。 PLL最初根据第一个时钟信号产生输出时钟信号。 当根据第一时钟信号产生的输出时钟信号的频率不在指定发送器所需的范围内时，PLL根据第二时钟信号产生输出时钟信号。

    COMMUNICATION SYSTEMS AND CLOCK GENERATION CIRCUITS THEREOF WITH REFERENCE SOURCE SWITCHING
    5.
    发明申请
    COMMUNICATION SYSTEMS AND CLOCK GENERATION CIRCUITS THEREOF WITH REFERENCE SOURCE SWITCHING 有权
    具有参考源切换的通信系统和时钟发生电路

    公开(公告)号：US20090296870A1

    公开(公告)日：2009-12-03

    申请号：US12410502

    申请日：2009-03-25

    申请人： Kuan-Hua Chao ,  Shiue-Shin Liu ,  Tse-Hsiang Hsu

    发明人： Kuan-Hua Chao ,  Shiue-Shin Liu ,  Tse-Hsiang Hsu

    IPC分类号： H04L7/00

    CPC分类号： H04L7/0091 ,  H04B15/02 ,  H04B2215/067 ,  H04L7/0083

    摘要： A clock generation circuit for a transmitter which transmits data according to an output clock signal is provided. The clock generation circuit include a clock generator and a phase locked loop (PLL). The clock generator generates a first clock signal. The PLL initially generates the output clock signal according to the first clock signal. When a frequency of the output clock signal generated according to the first clock signal is not within a range required for specification of the transmitter, the PLL switches to generate the output clock signal according to a second clock signal.

    摘要翻译： 提供了一种用于根据输出时钟信号发送数据的发送器的时钟发生电路。 时钟发生电路包括时钟发生器和锁相环（PLL）。 时钟发生器产生第一个时钟信号。 PLL最初根据第一个时钟信号产生输出时钟信号。 当根据第一时钟信号产生的输出时钟信号的频率不在指定发送器所需的范围内时，PLL切换以根据第二时钟信号产生输出时钟信号。

    CLOCK GENERATION DEVICES AND METHODS
    6.
    发明申请
    CLOCK GENERATION DEVICES AND METHODS 有权
    时钟生成装置和方法

    公开(公告)号：US20090168943A1

    公开(公告)日：2009-07-02

    申请号：US12328819

    申请日：2008-12-05

    申请人： Kuan-Hua Chao ,  Chuan Liu ,  Tse-Hsiang Hsu

    发明人： Kuan-Hua Chao ,  Chuan Liu ,  Tse-Hsiang Hsu

    IPC分类号： H04L7/00

    CPC分类号： H03L7/07

    摘要： A clock generation device provided for a transmitter is provided and comprises a clock generator, a calculator and a first phase locked loop (PLL) circuit. The clock generator generates a first clock signal. The calculator calculates a frequency difference between the first and second clock signals. The first PLL circuit generates an output clock signal according to a first reference clock signal related to the first clock signal, and a frequency of the output clock signal is changed according to the frequency difference. The transmitter transmits data according to the output clock signal.

    摘要翻译： 提供了一种用于发射机的时钟发生装置，包括时钟发生器，计算器和第一锁相环（PLL）电路。 时钟发生器产生第一个时钟信号。 计算器计算第一和第二时钟信号之间的频率差。 第一PLL电路根据与第一时钟信号相关的第一参考时钟信号产生输出时钟信号，并且输出时钟信号的频率根据频率差而改变。 发射机根据输出时钟信号发送数据。

    Clock generation devices and methods
    7.
    发明授权
    Clock generation devices and methods 有权
    时钟生成装置和方法

    公开(公告)号：US08619938B2

    公开(公告)日：2013-12-31

    申请号：US12328819

    申请日：2008-12-05

    申请人： Kuan-Hua Chao ,  Chuan Liu ,  Tse-Hsiang Hsu

    发明人： Kuan-Hua Chao ,  Chuan Liu ,  Tse-Hsiang Hsu

    IPC分类号： H04L7/00

    CPC分类号： H03L7/07

    摘要： A clock generation device provided for a transmitter is provided and comprises a clock generator, a calculator and a first phase locked loop (PLL) circuit. The clock generator generates a first clock signal. The calculator calculates a frequency difference between the first and second clock signals. The first PLL circuit generates an output clock signal according to a first reference clock signal related to the first clock signal, and a frequency of the output clock signal is changed according to the frequency difference. The transmitter transmits data according to the output clock signal.

    摘要翻译： 提供了一种用于发射机的时钟发生装置，包括时钟发生器，计算器和第一锁相环（PLL）电路。 时钟发生器产生第一个时钟信号。 计算器计算第一和第二时钟信号之间的频率差。 第一PLL电路根据与第一时钟信号相关的第一参考时钟信号产生输出时钟信号，并且输出时钟信号的频率根据频率差而改变。 发射机根据输出时钟信号发送数据。