公开(公告)号：US20080124886A1

公开(公告)日：2008-05-29

申请号：US11624220

申请日：2007-01-18

申请人： Tsung-De Lin ,  Cheng-Che Lee

发明人： Tsung-De Lin ,  Cheng-Che Lee

IPC分类号： H01L21/768

CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L27/10855

摘要： A method of fabricating a capacitor over bit line (COB) is provided. First, a substrate is provided and a plurality of word lines is formed on the substrate. Next, a plurality of landing plug contacts (LPCs) are formed between the word lines and a plurality of first contacts is then formed on the LPCs. Thereafter, a plurality of second contacts is formed on a first portions of the first contacts and a plurality of bit lines connecting a second portions of the first contacts is formed, simultaneously. An inter-layer dielectric (ILD) layer is formed on the substrate to cover the second contacts and the bit lines. Subsequently, a plurality of capacitors is formed in the ILD layer. Thus, the fabrication of the capacitor is simplified.

摘要翻译： 提供了一种通过位线（COB）制造电容器的方法。 首先，提供基板，并在基板上形成多个字线。 接下来，在字线之间形成多个着陆插头触点（LPC），然后在LPC上形成多个第一触点。 此后，多个第二触点形成在第一触点的第一部分上，同时形成连接第一触点的第二部分的多个位线。 在衬底上形成层间介电层（ILD）层以覆盖第二接触点和位线。 随后，在ILD层中形成多个电容器。 因此，简化了电容器的制造。

公开(公告)号：US20080124885A1

公开(公告)日：2008-05-29

申请号：US11624219

申请日：2007-01-18

申请人： Tsung-De Lin ,  Cheng-Che Lee

发明人： Tsung-De Lin ,  Cheng-Che Lee

IPC分类号： H01L21/768 ,  H01L21/62

CPC分类号： H01L28/91 ,  H01L27/10852

摘要： A method of fabricating an electrode of a capacitor is provided. A substrate is provided and a dielectric layer is then formed thereon. After that, one multilayer mask is formed on the dielectric layer to expose a portion of the dielectric layer, wherein the multilayer mask consists of at least two layers of materials having different etching rates respectively. The exposed dielectric layer is removed to form a trench, and then the dielectric layer is over-etched, so as to widen the inside diameter of the trench. Thereafter, a conductive layer is formed on the substrate, and thus the multilayer mask and a surface of the trench are covered with the conductive layer. The conductive layer except that in the trench is then removed so as to form the electrode of the capacitor. Therefore, it can prevent the conductive layer from generating more loss.

摘要翻译： 提供制造电容器的电极的方法。 提供衬底，然后在其上形成电介质层。 之后，在电介质层上形成一个多层掩模，以暴露介电层的一部分，其中多层掩模由分别具有不同蚀刻速率的至少两层材料构成。 去除暴露的电介质层以形成沟槽，然后对电介质层进行过蚀刻，以扩大沟槽的内径。 此后，在基板上形成导电层，因此多层掩模和沟槽的表面被导电层覆盖。 然后除去在沟槽中的导电层，以便形成电容器的电极。 因此，可以防止导电层产生更多的损耗。

公开(公告)号：US07635626B2

公开(公告)日：2009-12-22

申请号：US11767222

申请日：2007-06-22

申请人： Cheng-Che Lee ,  Tao-Yi Chang ,  Tsung-De Lin

发明人： Cheng-Che Lee ,  Tao-Yi Chang ,  Tsung-De Lin

IPC分类号： H01L21/8242

CPC分类号： H01L21/76897 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76855 ,  H01L27/10855 ,  H01L27/10888

摘要： A method of manufacturing a DRAM includes firstly providing a substrate. Many transistors are then formed on the substrate. Next, a first and a second LPCs are formed between the transistors. A first dielectric layer is then formed on the substrate, and a first opening exposing the first LPC is formed in the first dielectric layer. Thereafter, a barrier layer is formed on the first dielectric layer. Afterwards, a BLC is formed in the first opening, and a BL is formed on the first dielectric layer. A liner layer is then formed on a sidewall of the BL. Next, a second dielectric layer having a dry etching rate substantially equal to that of the liner layer and having a wet etching rate larger than that of the liner layer is formed on the substrate. Finally, an SNC is formed in the first and the second dielectric layers.

摘要翻译： 制造DRAM的方法包括首先提供衬底。 然后在衬底上形成许多晶体管。 接下来，在晶体管之间形成第一和第二LPC。 然后在衬底上形成第一电介质层，并且在第一电介质层中形成暴露第一LPC的第一开口。 此后，在第一电介质层上形成阻挡层。 之后，在第一开口中形成BLC，在第一介电层上形成BL。 然后在BL的侧壁上形成衬垫层。 接下来，在基板上形成具有与衬垫层的干蚀刻速率基本相等且具有大于衬层的湿刻蚀速率的干蚀刻速率的第二介质层。 最后，在第一和第二电介质层中形成SNC。

公开(公告)号：US07592219B2

公开(公告)日：2009-09-22

申请号：US11624220

申请日：2007-01-18

申请人： Tsung-De Lin ,  Cheng-Che Lee

发明人： Tsung-De Lin ,  Cheng-Che Lee

IPC分类号： H01L21/8242

CPC分类号： H01L28/60 ,  H01L27/10814 ,  H01L27/10855

摘要： A method of fabricating a capacitor over bit line (COB) is provided. First, a substrate is provided and a plurality of word lines is formed on the substrate. Next, a plurality of landing plug contacts (LPCs) are formed between the word lines and a plurality of first contacts is then formed on the LPCs. Thereafter, a plurality of second contacts is formed on a first portions of the first contacts and a plurality of bit lines connecting a second portions of the first contacts is formed, simultaneously. An inter-layer dielectric (ILD) layer is formed on the substrate to cover the second contacts and the bit lines. Subsequently, a plurality of capacitors is formed in the ILD layer. Thus, the fabrication of the capacitor is simplified.

摘要翻译： 提供了一种通过位线（COB）制造电容器的方法。 首先，提供基板，并在基板上形成多个字线。 接下来，在字线之间形成多个着陆插头触点（LPC），然后在LPC上形成多个第一触点。 此后，多个第二触点形成在第一触点的第一部分上，同时形成连接第一触点的第二部分的多个位线。 在衬底上形成层间介电层（ILD）层以覆盖第二接触点和位线。 随后，在ILD层中形成多个电容器。 因此，简化了电容器的制造。

公开(公告)号：US20080274602A1

公开(公告)日：2008-11-06

申请号：US11767222

申请日：2007-06-22

申请人： Cheng-Che Lee ,  Tao-Yi Chang ,  Tsung-De Lin

发明人： Cheng-Che Lee ,  Tao-Yi Chang ,  Tsung-De Lin

IPC分类号： H01L21/20

CPC分类号： H01L21/76897 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76855 ,  H01L27/10855 ,  H01L27/10888

摘要： A method of manufacturing a DRAM includes firstly providing a substrate. Many transistors are then formed on the substrate. Next, a first and a second LPCs are formed between the transistors. A first dielectric layer is then formed on the substrate, and a first opening exposing the first LPC is formed in the first dielectric layer. Thereafter, a barrier layer is formed on the first dielectric layer. Afterwards, a BLC is formed in the first opening, and a BL is formed on the first dielectric layer. A liner layer is then formed on a sidewall of the BL. Next, a second dielectric layer having a dry etching rate substantially equal to that of the liner layer and having a wet etching rate larger than that of the liner layer is formed on the substrate. Finally, an SNC is formed in the first and the second dielectric layers.

摘要翻译： 制造DRAM的方法包括首先提供衬底。 然后在衬底上形成许多晶体管。 接下来，在晶体管之间形成第一和第二LPC。 然后在衬底上形成第一电介质层，并且在第一电介质层中形成暴露第一LPC的第一开口。 此后，在第一电介质层上形成阻挡层。 之后，在第一开口中形成BLC，在第一介电层上形成BL。 然后在BL的侧壁上形成衬垫层。 接下来，在基板上形成具有与衬垫层的干蚀刻速率基本相等且具有大于衬层的湿刻蚀速率的干蚀刻速率的第二介质层。 最后，在第一和第二电介质层中形成SNC。

公开(公告)号：US07026171B2

公开(公告)日：2006-04-11

申请号：US10604246

申请日：2003-07-04

申请人： Y. Y. Chang ,  Shih-Liang Chou ,  L. H. Lee ,  Tsung-De Lin ,  Kou-Yow Tseng ,  Wen-Cheng Lien

发明人： Y. Y. Chang ,  Shih-Liang Chou ,  L. H. Lee ,  Tsung-De Lin ,  Kou-Yow Tseng ,  Wen-Cheng Lien

IPC分类号： H01L21/00 ,  H01L21/66

CPC分类号： H01L21/324 ,  H01L21/76801 ,  H01L22/20

摘要： A rapid thermal annealing (“RTA”) process providing for an RTA equipment is disclosed. The RTA equipment has a pyrometer providing for measuring an operation parameter, e.g., a temperature of the RTA process. The RTA process comprises steps of proceeding a first RTA step to a wafer in the RTA equipment, then comparing a measured value of the operation parameter with a reference range of value of the operation parameter, thereafter proceeding a second RTA step to the wafer in the RTA equipment when the measured value of the operation parameter is in between the reference range of value of the operation parameter. When the measured value of the operation parameter is out of the reference range of value of the operation parameter, the RTA equipment is turned off, and the wafer is unloaded from the RTA equipment and loaded into another RTA equipment to complete the RTA process.

摘要翻译： 公开了提供RTA设备的快速热退火（“RTA”）工艺。 RTA设备具有高温计，用于测量操作参数，例如RTA工艺的温度。 RTA方法包括以下步骤：在RTA设备中的晶片上进行第一RTA步骤，然后将操作参数的测量值与操作参数值的参考范围进行比较，然后在第二RTA步骤中进行第二RTA步骤 RTA设备当操作参数的测量值在操作参数值的参考范围之间时。 当操作参数的测量值超出操作参数值的参考范围时，RTA设备被关闭，晶片从RTA设备卸载并加载到另一个RTA设备中以完成RTA过程。

公开(公告)号：US06828208B2

公开(公告)日：2004-12-07

申请号：US10248538

申请日：2003-01-28

申请人： Tsung-De Lin ,  Hsiao-Kang Wang ,  Tian-Jue Hong ,  Shih-Liang Chou ,  Wen-Cheng Lien

发明人： Tsung-De Lin ,  Hsiao-Kang Wang ,  Tian-Jue Hong ,  Shih-Liang Chou ,  Wen-Cheng Lien

IPC分类号： H01L2176

CPC分类号： H01L21/76229

摘要： A method of fabricating a shallow trench isolation (STI) structure. A substrate is provided and then a pad oxide layer, a mask layer and a first trench are sequentially formed on the substrate. An insulation layer is formed inside the first trench and over the substrate. The insulation layer has a second trench in a location above the first trench. Thereafter, a conformal cap layer is formed over the insulation layer. The cap layer has a third trench in a location above the second trench. A reverse mask is formed over the cap layer covering the third trench. The cap layer and the insulation layer outside the reverse mask are removed to expose the upper surface of the mask layer. The reverse mask is removed and then the residual insulation layer outside the remaining cap layer and the trench are moved to expose the upper surface of the mask layer. Finally, the mask layer and the pad oxide layer are removed.

摘要翻译： 一种制造浅沟槽隔离（STI）结构的方法。 提供衬底，然后在衬底上依次形成衬垫氧化物层，掩模层和第一沟槽。 在第一沟槽内部和衬底上形成绝缘层。 绝缘层在第一沟槽上方的位置具有第二沟槽。 此后，在绝缘层上形成保形盖层。 盖层在第二沟槽上方的位置具有第三沟槽。 在覆盖第三沟槽的覆盖层上形成反向掩模。 去除覆盖层和反掩模外部的绝缘层以暴露掩模层的上表面。 去除反面掩模，然后移动剩余盖层和沟槽外部的残留绝缘层以暴露掩模层的上表面。 最后，去除掩模层和焊盘氧化物层。

公开(公告)号：US20100012996A1

公开(公告)日：2010-01-21

申请号：US12174067

申请日：2008-07-16

申请人： TSUNG DE LIN

发明人： TSUNG DE LIN

IPC分类号： H01L29/94

CPC分类号： H01L27/10855 ,  H01L21/76889

摘要： A dynamic random access memory structure comprises a substrate having a first diffusion region and a second diffusion region, a dielectric structure overlaying the substrate, a capacitor contact plug disposed in the dielectric structure and connected to the first diffusion region, a bit-line contact plug disposed in the dielectric structure and connected to the second diffusion region, a metal silicide disposed on the capacitor contact plug, and a capacitive structure disposed on the dielectric structure and connected to the metal silicide.

摘要翻译： 动态随机存取存储器结构包括具有第一扩散区和第二扩散区的衬底，覆盖衬底的电介质结构，设置在电介质结构中并连接到第一扩散区的电容器接触插塞，位线接触插塞 设置在电介质结构中并连接到第二扩散区，设置在电容器接触插塞上的金属硅化物，以及设置在电介质结构上并连接到金属硅化物的电容结构。