公开(公告)号：US20080213968A1

公开(公告)日：2008-09-04

申请号：US11766308

申请日：2007-06-21

Applicant: Cheng-Che Lee ,  Hui-Ling Chuang ,  Hsing-Wu Yeh

Inventor： Cheng-Che Lee ,  Hui-Ling Chuang ,  Hsing-Wu Yeh

IPC: H01L21/20

CPC classification number: H01L28/91 ,  H01L27/0207 ,  H01L27/10852

Abstract: A method for fabricating a capacitor includes firstly providing a substrate. A doped first dielectric layer and an undoped second dielectric layer are then formed on the substrate sequentially. Next, many trenches are formed in the first and the second dielectric layers. Afterwards, an ion implantation process is performed in the largest space between the adjacent trenches to form an ion-implanted region in a portion of the second dielectric layer in upper parts of the trenches. A wet etching process is then performed to remove a portion of the second dielectric layer in the ion-implanted region and a portion of the first dielectric layer at bottoms of the trenches. Thereafter, a first conductive layer and a capacitor dielectric layer are formed sequentially on surfaces of the trenches. Finally, a second conductive layer is formed in the trenches.

Abstract translation: 制造电容器的方法包括首先提供衬底。 然后依次在衬底上形成掺杂的第一介电层和未掺杂的第二介电层。 接下来，在第一和第二电介质层中形成许多沟槽。 然后，在相邻沟槽之间的最大空间中进行离子注入工艺，以在沟槽的上部的第二电介质层的一部分中形成离子注入区。 然后执行湿式蚀刻工艺以去除离子注入区域中的第二介电层的一部分和在沟槽底部的第一电介质层的一部分。 此后，在沟槽的表面上依次形成第一导电层和电容器电介质层。 最后，在沟槽中形成第二导电层。

公开(公告)号：US20080124885A1

公开(公告)日：2008-05-29

申请号：US11624219

申请日：2007-01-18

Applicant: Tsung-De Lin ,  Cheng-Che Lee

Inventor： Tsung-De Lin ,  Cheng-Che Lee

IPC: H01L21/768 ,  H01L21/62

CPC classification number: H01L28/91 ,  H01L27/10852

Abstract: A method of fabricating an electrode of a capacitor is provided. A substrate is provided and a dielectric layer is then formed thereon. After that, one multilayer mask is formed on the dielectric layer to expose a portion of the dielectric layer, wherein the multilayer mask consists of at least two layers of materials having different etching rates respectively. The exposed dielectric layer is removed to form a trench, and then the dielectric layer is over-etched, so as to widen the inside diameter of the trench. Thereafter, a conductive layer is formed on the substrate, and thus the multilayer mask and a surface of the trench are covered with the conductive layer. The conductive layer except that in the trench is then removed so as to form the electrode of the capacitor. Therefore, it can prevent the conductive layer from generating more loss.

Abstract translation: 提供制造电容器的电极的方法。 提供衬底，然后在其上形成电介质层。 之后，在电介质层上形成一个多层掩模，以暴露介电层的一部分，其中多层掩模由分别具有不同蚀刻速率的至少两层材料构成。 去除暴露的电介质层以形成沟槽，然后对电介质层进行过蚀刻，以扩大沟槽的内径。 此后，在基板上形成导电层，因此多层掩模和沟槽的表面被导电层覆盖。 然后除去在沟槽中的导电层，以便形成电容器的电极。 因此，可以防止导电层产生更多的损耗。

公开(公告)号：US07030441B2

公开(公告)日：2006-04-18

申请号：US10986877

申请日：2004-11-15

Applicant: Yung-Hsien Wu ,  Cheng-Che Lee

Inventor： Yung-Hsien Wu ,  Cheng-Che Lee

IPC: H01L29/76 ,  H01L29/94

CPC classification number: H01L21/02326 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/10835 ,  H01L27/1087 ,  H01L29/66181

Abstract: A capacitor dielectric structure of a deep trench capacitor for a DRAM cell is disclosed. A semiconductor silicon substrate is provided with a deep trench. Silicon nitride deposition is used to form a silicon nitride layer on the sidewall and bottom of the deep trench. An oxynitride process with wet oxidation and N2O reactive gas is used to form an oxynitride layer on the silicon nitride layer. A post oxynitride growth annealing is performed on the oxynitride layer.

Abstract translation: 公开了用于DRAM单元的深沟槽电容器的电容器电介质结构。 半导体硅衬底设置有深沟槽。 氮化硅沉积用于在深沟槽的侧壁和底部上形成氮化硅层。 使用具有湿氧化和N2O反应气体的氧氮化物工艺在氮化硅层上形成氧氮化物层。 在氧氮化物层上进行氧氮化后生长退火。

公开(公告)号：US20050062100A1

公开(公告)日：2005-03-24

申请号：US10986877

申请日：2004-11-15

Applicant: Yung-Hsien Wu ,  Cheng-Che Lee

Inventor： Yung-Hsien Wu ,  Cheng-Che Lee

IPC: H01L21/314 ,  H01L21/318 ,  H01L21/334 ,  H01L21/8242 ,  H01L27/108 ,  H01L29/792 ,  H01L29/76 ,  H01L31/062

CPC classification number: H01L21/02326 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/10835 ,  H01L27/1087 ,  H01L29/66181

Abstract: A capacitor dielectric structure of a deep trench capacitor for a DRAM cell. A semiconductor silicon substrate is provided wit a deep trench. Silicon nitride deposition is used to form a silicon nitride layer on the sidewall and bottom of the deep trench. An oxynitride process with wet oxidation and N2O reactive gas is used to form an oxynitride layer on the silicon nitride layer. A post oxynitride growth annealing is performed on the oxynitride layer.

Abstract translation: 用于DRAM单元的深沟槽电容器的电容器电介质结构。 半导体硅衬底具有深沟槽。 氮化硅沉积用于在深沟槽的侧壁和底部上形成氮化硅层。 使用具有湿氧化和N2O反应气体的氧氮化物工艺在氮化硅层上形成氧氮化物层。 在氧氮化物层上进行氧氮化后生长退火。

公开(公告)号：US06835630B2

公开(公告)日：2004-12-28

申请号：US10376230

申请日：2003-03-03

Applicant: Yung-Hsien Wu ,  Cheng-Che Lee

Inventor： Yung-Hsien Wu ,  Cheng-Che Lee

IPC: H01L218234

CPC classification number: H01L21/02326 ,  H01L21/0214 ,  H01L21/0217 ,  H01L21/02337 ,  H01L21/3144 ,  H01L21/3185 ,  H01L27/10835 ,  H01L27/1087 ,  H01L29/66181

Abstract: A capacitor dielectric structure of a deep trench capacitor for a DRAM cell. A semiconductor silicon substrate is provided wit a deep trench. Silicon nitride deposition is used to form a silicon nitride layer on the sidewall and bottom of the deep trench. An oxynitride process with wet oxidation and N2O reactive gas is used to form an oxynitride layer on the silicon nitride layer. A post oxynitride growth annealing is performed on the oxynitride layer.

Abstract translation: 用于DRAM单元的深沟槽电容器的电容器电介质结构。 半导体硅衬底具有深沟槽。 氮化硅沉积用于在深沟槽的侧壁和底部上形成氮化硅层。 使用具有湿氧化和N2O反应气体的氧氮化物工艺在氮化硅层上形成氧氮化物层。 在氧氮化物层上进行氧氮化后生长退火。

公开(公告)号：US06291030B1

公开(公告)日：2001-09-18

申请号：US09468720

申请日：1999-12-21

Applicant: Chung-Pei Chao ,  Cheng-Che Lee

Inventor： Chung-Pei Chao ,  Cheng-Che Lee

IPC: H05H124

CPC classification number: H01L21/7682 ,  H01L21/31612

Abstract: A method for forming a metal interconnect having a plurality of metal lines and an interlayer dielectric is disclosed. The metal interconnect has a decreased capacitance between the metal lines of the metal interconnect. First, a metal interconnect is formed onto a substrate. A first HDPCVD oxide layer is formed over the metal interconnect. A second HDPCVD oxide layer is formed over the first HDPCVD oxide layer, the second HDPCVD oxide layer being formed such that air gaps are formed between the metal lines of the metal interconnect. Furthermore, a third HDPCVD oxide layer may be formed over the second HDPCVD oxide layer, the third HDPCVD oxide formed using a sputter to deposition ratio higher than that used to form the second HDPCVD oxide layer.

Abstract translation: 公开了一种用于形成具有多个金属线和层间电介质的金属互连的方法。 金属互连在金属互连的金属线之间具有减小的电容。 首先，在基板上形成金属配线。 第一HDPCVD氧化物层形成在金属互连上。 在第一HDPCVD氧化物层上形成第二HDPCVD氧化物层，形成第二HDPCVD氧化物层，使得在金属互连的金属线之间形成气隙。 此外，可以在第二HDPCVD氧化物层上形成第三HDPCVD氧化物层，使用高于用于形成第二HDPCVD氧化物层的溅射沉积比形成第三HDPCVD氧化物。

公开(公告)号：US08505819B2

公开(公告)日：2013-08-13

申请号：US13281461

申请日：2011-10-26

Applicant: Cheng-Che Lee ,  Wen-Hai Tsai ,  Keng-Hao Chang ,  Chiu-Chin Yang ,  Waken Chen ,  Jih-Hsin Yeh

Inventor： Cheng-Che Lee ,  Wen-Hai Tsai ,  Keng-Hao Chang ,  Chiu-Chin Yang ,  Waken Chen ,  Jih-Hsin Yeh

IPC: G06K5/00

CPC classification number: B01L3/5023 ,  B01L2200/04 ,  B01L2300/021 ,  B01L2300/0825 ,  G01N33/48771

Abstract: The present invention discloses a biological measuring device with auto coding capabilities. In accordance with one embodiment of the present invention, the biological measuring device with auto coding capabilities includes a test strip having a substrate and at least a first contact pad and a second contact pad provided on the substrate; and a code reader having at least a first metal pin and a second metal pin to couple to the first contact pad and the second contact pad to obtain coding information associated with the test strip, wherein the code reader is capable of reading the coding information based on a movement of the test strip before the test strip is placed still in relation to the code reader for a proper reading of a sample.

Abstract translation: 本发明公开了一种具有自动编码能力的生物测量装置。 根据本发明的一个实施例，具有自动编码能力的生物测量装置包括具有衬底和至少第一接触焊盘和设置在衬底上的第二接触焊盘的测试条; 以及代码阅读器，具有至少第一金属引脚和第二金属引脚，以耦合到所述第一接触焊盘和所述第二接触焊盘以获得与所述测试条相关联的编码信息，其中所述代码读取器能够读取基于编码信息的编码信息 在测试条被放置在仍然相对于代码阅读器以正确读取样本之前的测试条的移动。

公开(公告)号：US20100084261A1

公开(公告)日：2010-04-08

申请号：US12246508

申请日：2008-10-07

Applicant: Kun-Yi Lee ,  Wei-Ching Chuang ,  Yen-Juei Lin ,  Cheng-Che Lee ,  Wei-Yu Lee

Inventor： Kun-Yi Lee ,  Wei-Ching Chuang ,  Yen-Juei Lin ,  Cheng-Che Lee ,  Wei-Yu Lee

IPC: C23C14/00

CPC classification number: G02B6/124 ,  G02B6/138

Abstract: The present invention discloses a method for fabricating polymeric wavelength filter, which method for forming gratings patterns on the UV polymer involves three processing steps. First, a gratings pattern is holographically exposed using a two-beam interference pattern on a positive photo-resister film. A 20-nm-thick nickel thin film is then sputtered onto the positive photo-resister film to form a nickel mold. This nickel mold on the photo-resister film then can be subsequently used to transfer the final gratings pattern onto a UV cure epoxy polymer. Whereby, a polymer film can be spun coated on the cure epoxy substrate so as to simplify the fabrication process for obtaining a polymer wavelength filter with good aspect ratio of gratings pattern.

Abstract translation: 本发明公开了一种用于制造聚合物波长滤光器的方法，其中在UV聚合物上形成光栅图案的方法涉及三个处理步骤。 首先，在正光阻膜上使用双光束干涉图案将光栅图案全息曝光。 然后将20nm厚的镍薄膜溅射到正光电阻膜上以形成镍模。 然后可以将光电阻膜上的该镍模具随后用于将最终光栅图案转印到UV固化环氧聚合物上。 由此，可以将聚合物膜旋涂在固化环氧树脂基板上，以简化用于获得具有良好的光栅长宽比的聚合物波长滤光器的制造工艺。

公开(公告)号：US07635626B2

公开(公告)日：2009-12-22

申请号：US11767222

申请日：2007-06-22

Applicant: Cheng-Che Lee ,  Tao-Yi Chang ,  Tsung-De Lin

Inventor： Cheng-Che Lee ,  Tao-Yi Chang ,  Tsung-De Lin

IPC: H01L21/8242

CPC classification number: H01L21/76897 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76846 ,  H01L21/76855 ,  H01L27/10855 ,  H01L27/10888

Abstract: A method of manufacturing a DRAM includes firstly providing a substrate. Many transistors are then formed on the substrate. Next, a first and a second LPCs are formed between the transistors. A first dielectric layer is then formed on the substrate, and a first opening exposing the first LPC is formed in the first dielectric layer. Thereafter, a barrier layer is formed on the first dielectric layer. Afterwards, a BLC is formed in the first opening, and a BL is formed on the first dielectric layer. A liner layer is then formed on a sidewall of the BL. Next, a second dielectric layer having a dry etching rate substantially equal to that of the liner layer and having a wet etching rate larger than that of the liner layer is formed on the substrate. Finally, an SNC is formed in the first and the second dielectric layers.

Abstract translation: 制造DRAM的方法包括首先提供衬底。 然后在衬底上形成许多晶体管。 接下来，在晶体管之间形成第一和第二LPC。 然后在衬底上形成第一电介质层，并且在第一电介质层中形成暴露第一LPC的第一开口。 此后，在第一电介质层上形成阻挡层。 之后，在第一开口中形成BLC，在第一介电层上形成BL。 然后在BL的侧壁上形成衬垫层。 接下来，在基板上形成具有与衬垫层的干蚀刻速率基本相等且具有大于衬层的湿刻蚀速率的干蚀刻速率的第二介质层。 最后，在第一和第二电介质层中形成SNC。

公开(公告)号：US20090136180A1

公开(公告)日：2009-05-28

申请号：US11945973

申请日：2007-11-27

Applicant: Kun-Yi Lee ,  Wei-Ching Chuang ,  Kuen-Cherng Lin ,  Cheng-Che Lee ,  Wei-Yu Lee

Inventor： Kun-Yi Lee ,  Wei-Ching Chuang ,  Kuen-Cherng Lin ,  Cheng-Che Lee ,  Wei-Yu Lee

IPC: G02B6/26 ,  B29D11/00

CPC classification number: B29D11/00663 ,  G02B6/124 ,  G02B6/138

Abstract: The present invention discloses a method for fabricating polymer wavelength filter with high-resolution periodical structure, which comprises following steps: (a) a positive photo-resister film is coated on a substrate; (b) a grating pattern is holographically exposed on the positive photo-resister film; (c) the photo-resister film is coated with a negative photo-resister film; (d) the sample is exposed by UV light; (e) develops the sample to obtain a negative waveguide on the photo-resister film having gratings pattern on its bottom to be a waveguide mold; (f) coats a diluted PDMS film on the patterned waveguide mold; (g) bakes the PDMS film to be cured, and peels off from the waveguide mold to be a PDMS mold; (h) places a spacer between the PDMS mold and a thin glass slide to form a first tunnel; (i) injects a precure first UV polymer into the first tunnel; (j) cures the first UV polymer under a broadband UV light; (k) separates the first UV polymer when fully cured, a hardened first UV polymer is formed having a groove with gratings pattern at its bottom for forming a cladding layer of the polymer wavelength filter; (l) a thin layer of a polydimethylsiloxane is spun onto a glass slide, and the glass slide is placed over the groove of the first UV polymer; (m) a second UV polymer is injected into the groove of the first UV polymer; and (n) the second UV polymer is cured by exposing the UV light, and to form the core of the waveguide in the groove of the first UV polymer to finally be the polymer wavelength filter.

Abstract translation: 本发明公开了一种制造具有高分辨率周期结构的聚合物波长滤波器的方法，包括以下步骤：（a）将正光阻膜涂覆在基片上; （b）光栅图案被全息曝光在正光敏膜上; （c）光阻膜用负光电阻膜涂覆; （d）样品通过紫外光曝光; （e）开发样品以在其底部具有作为波导模具的光栅图案的光电阻膜上获得负波导; （f）在图案化的波导模具上涂覆稀释的PDMS膜; （g）烘烤要固化的PDMS膜，并从波导模具剥离成PDMS模具; （h）在PDMS模具和薄玻璃滑块之间放置间隔件以形成第一隧道; （i）将预固化的第一UV聚合物注入第一隧道; （j）在宽带UV光下固化第一UV聚合物; （k）在完全固化时分离第一UV聚合物，形成具有在其底部具有格栅图案的凹槽的硬化的第一UV聚合物，以形成聚合物波长滤光器的包层; （1）将一薄层的聚二甲基硅氧烷旋转到载玻片上，并将载玻片置于第一UV聚合物的槽上; （m）将第二UV聚合物注入第一UV聚合物的凹槽中; 和（n）第二UV聚合物通过暴露UV光而固化，并在第一UV聚合物的沟槽中形成波导的芯，最终成为聚合物波长滤光器。