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    Dram cell pair and dram memory cell array
    1.
    发明授权
    Dram cell pair and dram memory cell array 失效
    戏剧单元对和阵容记忆体单元阵列

    公开(公告)号：US07301192B2

    公开(公告)日：2007-11-27

    申请号：US11222273

    申请日：2005-09-08

    申请人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Grüning Von Schwerin ,  Till Schloesser ,  Rolf Weis

    发明人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Grüning Von Schwerin ,  Till Schloesser ,  Rolf Weis

    IPC分类号： H01L27/108

    CPC分类号： H01L27/108 ,  G11C11/404 ,  H01L27/0207 ,  H01L27/10808 ,  H01L27/10829 ,  H01L29/785

    摘要： Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.

    摘要翻译： 堆叠和沟槽存储单元被提供在DRAM存储单元阵列中。 堆叠和沟槽存储单元布置成形成相同的单元对，每个单元对具有沟槽电容器，堆叠电容器和半导体鳍片，其中形成用于寻址沟槽和堆叠电容器的两个选择晶体管的有源区。 半导体鳍片沿纵向连续布置以形成单元行，并且在这种布置中，在每种情况下都是沟槽电容器彼此间隔开。 相邻的单元行通过沟槽隔离器结构彼此分离，并且相对于彼此相对于单元对的长度的一半偏移。 半导体鳍片被至少两个相对于单元行正交的有源字线交叉，用于寻址在半导体鳍片中实现的选择晶体管。

    Transistor structure with a curved channel, memory cell and memory cell array for DRAMs, and methods for fabricating a DRAM
    4.
    发明授权
    Transistor structure with a curved channel, memory cell and memory cell array for DRAMs, and methods for fabricating a DRAM 有权
    具有用于DRAM的弯曲通道，存储单元和存储单元阵列的晶体管结构以及用于制造DRAM的方法

    公开(公告)号：US07279742B2

    公开(公告)日：2007-10-09

    申请号：US11024935

    申请日：2004-12-30

    申请人： Ulrike Grüning-Von Schwerin

    发明人： Ulrike Grüning-Von Schwerin

    IPC分类号： H01L27/108 ,  H01L29/94

    CPC分类号： H01L27/10823 ,  H01L27/10855 ,  H01L27/10876 ,  H01L27/10879 ,  H01L27/10888 ,  H01L27/10891 ,  H01L29/66795 ,  H01L29/785

    摘要： A transistor structure having source/drain regions arranged in a horizontal plane along an x axis has a recess structure, which separates the two source/drain regions from one another and increases the effective channel length Leff of the transistor structure. A vertical gate electrode with respect to the horizontal plane extends along the x axis and in this case encloses an active zone of the transistor structure from two sides or completely. The effective channel width Weff is dependent on the depth to which the gate electrode is formed. A memory cell having a selection transistor in accordance with the transistor structure has both a low leakage current and a good switching behavior. By a suitable integration concept, the transistor structure is integrated into a memory cell array of a DRAM having hole trench capacitors or stacked capacitors.

    摘要翻译： 具有沿着x轴布置在水平面中的源极/漏极区域的晶体管结构具有凹陷结构，其将两个源极/漏极区彼此分离并且增加了源极/漏极区域的有效沟道长度L eff 晶体管结构。 相对于水平面的垂直栅极电极沿x轴延伸，并且在这种情况下，从两侧或完全封闭晶体管结构的有源区。 有效沟道宽度W eff取决于形成栅电极的深度。 具有根据晶体管结构的选择晶体管的存储单元具有低漏电流和良好的开关行为。 通过合适的集成概念，晶体管结构集成到具有空穴沟槽电容器或堆叠电容器的DRAM的存储单元阵列中。

    Semiconductor memory cell and method for fabricating the memory cell
    5.
    发明授权
    Semiconductor memory cell and method for fabricating the memory cell 失效
    半导体存储单元及其制造方法

    公开(公告)号：US06828192B2

    公开(公告)日：2004-12-07

    申请号：US10657928

    申请日：2003-09-10

    申请人： Wolfgang Gustin ,  Ulrike Grüning-Von Schwerin ,  Dietmar Temmler ,  Martin Schrems ,  Stefan Rongen ,  Rudolf Strasser

    发明人： Wolfgang Gustin ,  Ulrike Grüning-Von Schwerin ,  Dietmar Temmler ,  Martin Schrems ,  Stefan Rongen ,  Rudolf Strasser

    IPC分类号： H01L218242

    CPC分类号： H01L27/10867 ,  H01L27/10873

    摘要： A trench capacitor is formed in a trench, which is disposed in a substrate. The trench is filled with a conductive trench filling which functions as an inner capacitor electrode. An epitaxial layer is grown on the sidewall of the trench on the substrate. A buried strap is disposed between the conductive trench filling with the second intermediate layer and the epitaxially grown layer. A dopant outdiffusion formed from the buried strap is disposed in the epitaxially grown layer. Through the epitaxially grown layer, the dopant outdiffusion is further removed from a selection transistor disposed beside the trench, as a result of which it is possible to avoid short-channel effects in the selection transistor.

    摘要翻译： 在沟槽中形成沟槽电容器，其设置在基板中。 沟槽填充有用作内部电容器电极的导电沟槽填充物。 在衬底上的沟槽的侧壁上生长外延层。 掩埋带设置在填充有第二中间层的导电沟槽和外延生长层之间。 在外延生长层中设置从掩埋带形成的掺杂剂外扩散。 通过外延生长层，从布置在沟槽旁边的选择晶体管进一步去除掺杂剂扩散，结果可以避免选择晶体管中的短沟道效应。