利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

112 条记录 (耗时 0.026 秒)

    Dram cell pair and dram memory cell array
    1.
    发明授权
    Dram cell pair and dram memory cell array 失效
    戏剧单元对和阵容记忆体单元阵列

    公开(公告)号：US07301192B2

    公开(公告)日：2007-11-27

    申请号：US11222273

    申请日：2005-09-08

    申请人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Grüning Von Schwerin ,  Till Schloesser ,  Rolf Weis

    发明人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Grüning Von Schwerin ,  Till Schloesser ,  Rolf Weis

    IPC分类号： H01L27/108

    CPC分类号： H01L27/108 ,  G11C11/404 ,  H01L27/0207 ,  H01L27/10808 ,  H01L27/10829 ,  H01L29/785

    摘要： Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.

    摘要翻译： 堆叠和沟槽存储单元被提供在DRAM存储单元阵列中。 堆叠和沟槽存储单元布置成形成相同的单元对，每个单元对具有沟槽电容器，堆叠电容器和半导体鳍片，其中形成用于寻址沟槽和堆叠电容器的两个选择晶体管的有源区。 半导体鳍片沿纵向连续布置以形成单元行，并且在这种布置中，在每种情况下都是沟槽电容器彼此间隔开。 相邻的单元行通过沟槽隔离器结构彼此分离，并且相对于彼此相对于单元对的长度的一半偏移。 半导体鳍片被至少两个相对于单元行正交的有源字线交叉，用于寻址在半导体鳍片中实现的选择晶体管。

    Dram cell pair and dram memory cell array
    2.
    发明申请
    Dram cell pair and dram memory cell array 失效
    戏剧单元对和阵容记忆体单元阵列

    公开(公告)号：US20060076602A1

    公开(公告)日：2006-04-13

    申请号：US11222273

    申请日：2005-09-08

    申请人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Schwerin ,  Till Schloesser ,  Rolf Weis

    发明人： Johann Harter ,  Wolfgang Mueller ,  Wolfgang Bergner ,  Ulrike Schwerin ,  Till Schloesser ,  Rolf Weis

    IPC分类号： H01L29/94 ,  H01L21/8244

    CPC分类号： H01L27/108 ,  G11C11/404 ,  H01L27/0207 ,  H01L27/10808 ,  H01L27/10829 ,  H01L29/785

    摘要： Stack and trench memory cells are provided in a DRAM memory cell array. The stack and trench memory cells are arranged so as to form identical cell pairs each having a trench capacitor, a stack capacitor and a semiconductor fin, in which the active areas of two select transistors for addressing the trench and stack capacitors are formed. The semiconductor fins are arranged in succession in the longitudinal direction to form cell rows and in this arrangement are spaced apart from one another by in each case a trench capacitor. Respectively adjacent cell rows are separated from one another by trench isolator structures and are offset with respect to one another by half the length of a cell pair. The semiconductor fins are crossed by at least two active word lines, which are orthogonal with respect to the cell rows, for addressing the select transistors realized in the semiconductor fin.

    摘要翻译： 堆叠和沟槽存储单元被提供在DRAM存储单元阵列中。 堆叠和沟槽存储单元布置成形成相同的单元对，每个单元对具有沟槽电容器，堆叠电容器和半导体鳍片，其中形成用于寻址沟槽和堆叠电容器的两个选择晶体管的有源区。 半导体鳍片沿纵向连续布置以形成单元行，并且在这种布置中，在每种情况下都是沟槽电容器彼此间隔开。 相邻的单元行通过沟槽隔离器结构彼此分离，并且相对于彼此相对于单元对的长度的一半偏移。 半导体鳍片被至少两个相对于单元行正交的有源字线交叉，用于寻址在半导体鳍片中实现的选择晶体管。

    DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same
    4.
    发明申请
    DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same 失效
    具有垂直存储单元的DRAM单元阵列和存储单元布置及其制造方法

    公开(公告)号：US20050083724A1

    公开(公告)日：2005-04-21

    申请号：US10898706

    申请日：2004-07-23

    申请人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

    发明人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

    IPC分类号： G11C11/34 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L27/10867 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

    摘要： Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.

    摘要翻译： 每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。 通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏​​极电容的减小以及栅电极和漏电极之间的漏电流 较低的源极/漏极区域。 用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。 单元晶体管的上源/漏区通过接触孔注入而形成。

    DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM
    6.
    发明申请
    DRAM cell array having vertical memory cells and methods for fabricating a DRAM cell array and a DRAM 审中-公开
    具有垂直存储单元的DRAM单元阵列和用于制造DRAM单元阵列和DRAM的方法

    公开(公告)号：US20050088895A1

    公开(公告)日：2005-04-28

    申请号：US10897687

    申请日：2004-07-23

    申请人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller ,  Joachim Nuetzel ,  Klaus Muemmler

    发明人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller ,  Joachim Nuetzel ,  Klaus Muemmler

    IPC分类号： G11C11/34

    CPC分类号： H01L27/10841 ,  H01L27/10867

    摘要： Memory cells having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation with subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor, which consequently results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A gate conductor layer structure is applied and there are formed, from the gate conductor layer structure, in a controlled transistor array, gate electrode structures of control transistors and, in the cell array, a body connection structure for the connection of body regions of the cell transistors.

    摘要翻译： 在DRAM的单元阵列中设置具有单元电容器和单元晶体管的存储单元，其被布置在垂直单元结构中。 通过深度注入或随后的硅的外延生长的浅注入，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对准，这因此导致栅极/漏​​极电容的减小以及栅电极和漏极电极之间的漏电流 较低的源极/漏极区域。 施加栅极导体层结构，并且从栅极导体层结构形成受控晶体管阵列，控制晶体管的栅极电极结构以及在单元阵列中形成用于连接主体区域的主体连接结构 单元晶体管。

    DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same
    7.
    发明授权
    DRAM cell array and memory cell arrangement having vertical memory cells and methods for fabricating the same 失效
    具有垂直存储单元的DRAM单元阵列和存储单元布置及其制造方法

    公开(公告)号：US07141845B2

    公开(公告)日：2006-11-28

    申请号：US10898706

    申请日：2004-07-23

    申请人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

    发明人： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10867 ,  H01L27/10841 ,  H01L27/10876 ,  H01L27/10888 ,  H01L27/10891

    摘要： Memory cells each having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation and subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor and this results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A body connection plate for the connection of the channel regions is applied to the substrate surface and contact holes are introduced into the body connection plate. Upper source/drain regions of the cell transistors are formed by implantation through the contact holes.

    摘要翻译： 每个具有单元电容器和单元晶体管的存储单元被布置在垂直单元结构中，被提供在DRAM的单元阵列中。 通过深度注入或浅注入和随后的硅的外延生长，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对齐，并且这导致栅极/漏​​极电容的减小以及栅电极和漏电极之间的漏电流 较低的源极/漏极区域。 用于连接通道区域的主体连接板被施加到基板表面，并且接触孔被引入主体连接板。 单元晶体管的上源/漏区通过接触孔注入而形成。

    Integrated circuit having a memory cell array and method of forming an integrated circuit
    8.
    发明授权
    Integrated circuit having a memory cell array and method of forming an integrated circuit 失效
    具有存储单元阵列的集成电路和形成集成电路的方法

    公开(公告)号：US07642572B2

    公开(公告)日：2010-01-05

    申请号：US11735164

    申请日：2007-04-13

    申请人： Martin Popp ,  Till Schloesser ,  Ulrike Gruening-von Schwerin ,  Rolf Weis

    发明人： Martin Popp ,  Till Schloesser ,  Ulrike Gruening-von Schwerin ,  Rolf Weis

    IPC分类号： H01L27/108

    CPC分类号： H01L27/10817 ,  G11C5/063 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

    摘要： An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75.

    摘要翻译： 公开了一种具有存储单元阵列的集成电路和形成集成电路的方法。 一个实施例提供沿着第一方向行进的位线，沿着基本上垂直于第一方向的第二方向行进的字线，有效区域和位线接触。 位线触点被布置成沿着第二方向延伸的列，并且以沿第一方向延伸的列布置。 相邻位线之间的距离为DL，相邻位线触点之间的距离为DC，DC平行于第一方向测量。 以下关系成立：1 / 2.25 <= DL / DC <= 1 / 1.75。

    Transistor, memory cell array and method of manufacturing a transistor
    9.
    发明授权
    Transistor, memory cell array and method of manufacturing a transistor 失效
    晶体管，存储单元阵列及制造晶体管的方法

    公开(公告)号：US07635893B2

    公开(公告)日：2009-12-22

    申请号：US11128782

    申请日：2005-05-13

    申请人： Rolf Weis ,  Till Schloesser ,  Ulrike Gruening von Schwerin

    发明人： Rolf Weis ,  Till Schloesser ,  Ulrike Gruening von Schwerin

    IPC分类号： H01L29/772

    CPC分类号： H01L27/10894 ,  H01L27/10808 ,  H01L27/10838 ,  H01L27/10876 ,  H01L27/10879 ,  H01L29/66621 ,  H01L29/7834 ,  H01L29/7851

    摘要： A transistor, memory cell array and method of manufacturing a transistor are disclosed. In one embodiment, the invention refers to a transistor, which is formed at least partially in a semiconductor substrate, comprising a first and a second source/drain regions, a channel region connecting said first and second source/drain regions, said channel region being disposed in said semiconductor substrate, and a gate electrode disposed along said channel region and being electrically insulated from said channel region, for controlling an electrical current flowing between said first and second source/drain regions, wherein said channel region comprises a fin-region in which the channel has the shape of a ridge, said ridge comprising a top side and two lateral sides in a cross section perpendicular to a line connecting said first and second source/drain regions, wherein said top side is disposed beneath a surface of said semiconductor substrate and said gate electrode is disposed along said top side and said two lateral sides.

    摘要翻译： 公开了晶体管，存储单元阵列和制造晶体管的方法。 在一个实施例中，本发明涉及至少部分地形成在半导体衬底中的晶体管，包括第一和第二源极/漏极区域，连接所述第一和第二源极/漏极区域的沟道区域，所述沟道区域是 设置在所述半导体衬底中的栅电极以及沿着所述沟道区设置并与所述沟道区电绝缘的栅极，用于控制在所述第一和第二源/漏区之间流动的电流，其中所述沟道区包括 所述通道具有脊的形状，所述脊包括垂直于连接所述第一和第二源极/漏极区的线的横截面中的顶侧和两个侧边，其中所述顶侧设置在所述半导体的表面下方 基板和所述栅电极沿着所述顶侧和所述两个横向侧面设置。

    INTEGRATED CIRCUIT HAVING A MEMORY CELL ARRAY AND METHOD OF FORMING AN INTEGRATED CIRCUIT
    10.
    发明申请
    INTEGRATED CIRCUIT HAVING A MEMORY CELL ARRAY AND METHOD OF FORMING AN INTEGRATED CIRCUIT 失效
    具有存储单元阵列的集成电路和形成集成电路的方法

    公开(公告)号：US20080253160A1

    公开(公告)日：2008-10-16

    申请号：US11735164

    申请日：2007-04-13

    申请人： Martin Popp ,  Till Schloesser ,  Ulrike Gruening-von Schwerin ,  Rolf Weis

    发明人： Martin Popp ,  Till Schloesser ,  Ulrike Gruening-von Schwerin ,  Rolf Weis

    IPC分类号： G11C5/06 ,  H01L21/82

    CPC分类号： H01L27/10817 ,  G11C5/063 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885

    摘要： An integrated circuit having a memory cell array and a method of forming an integrated circuit is disclosed. One embodiment provides bitlines running along a first direction, wordlines running along a second direction substantially perpendicular to the first direction, active areas and bitline contacts. The bitline contacts are arranged in columns extending in the second direction and in rows extending in the first direction. A distance between neighboring bitlines is DL, and a distance between neighboring bitline contacts is DC, DC being measured parallel to the first direction. The following relation holds: 1/2.25≦DL/DC≦1/1.75.

    摘要翻译： 公开了一种具有存储单元阵列的集成电路和形成集成电路的方法。 一个实施例提供沿着第一方向行进的位线，沿着基本上垂直于第一方向的第二方向行进的字线，有效区域和位线接触。 位线触点被布置成沿着第二方向延伸的列，并且以沿第一方向延伸的列布置。 相邻位线之间的距离为DL，相邻位线触点之间的距离为DC，DC平行于第一方向测量。 以下关系成立：1 / 2.25 <= DL / DC <= 1 / 1.75。