公开(公告)号：US07989308B2

公开(公告)日：2011-08-02

申请号：US10599726

申请日：2005-04-07

Applicant: Ralf Lerner ,  Uwe Eckoldt ,  Thomas Oetzel

Inventor： Ralf Lerner ,  Uwe Eckoldt ,  Thomas Oetzel

IPC: H01L27/12

CPC classification number: H01L21/76235

Abstract: The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically chip regions having different potentials from each other with the aid of isolation trenches (10). In order to prevent voltage rises at sharp edges on the bottom of the isolation trenches, said edges are rounded in a simple process, part of the insulating layer (2) being isotropically etched.

Abstract translation: 本发明的目的是将低电压逻辑元件和高压功率元件集成在同一个硅电路中。 所述目的通过借助于隔离沟槽（10）彼此具有不同电位的介电芯片区域实现。 为了防止隔离沟底部的尖锐边缘处的电压上升，所述边缘以简单的工艺被倒圆，绝缘层（2）的一部分被各向同性地蚀刻。

公开(公告)号：US07625805B2

公开(公告)日：2009-12-01

申请号：US10586621

申请日：2005-01-31

Applicant: Ralf Lerner ,  Uwe Eckoldt

Inventor： Ralf Lerner ,  Uwe Eckoldt

IPC: H01L21/76 ,  H01L21/461 ,  H01L21/302 ,  H01L21/311

CPC classification number: H01L21/76283 ,  H01L21/76224 ,  H01L21/76286 ,  H01L21/763

Abstract: Trenches are formed in an SOI wafer to isolate low-voltage and high-voltage elements in the wafer. The isolation trenches are formed with trench coverings that do not protrude above the trenches. Vertical in-trench and horizontal out-of-trench isolation layers are formed and the trenches are then filled to above the planar surface formed by the isolating layers. The filling is planarized and a portion of the filling located in the trench interior is removed. A portion of the isolation layers are then removed and a portion of the filling is removed so that the filler and the isolation layers in the trenches are at about the same level. A covering layer is then deposited. The covering layer extends above the surface of the wafer and into the trenches down to the filler and the isolation layers. The covering layer is additionally planarized to about the top of the trenches.

Abstract translation: 沟槽形成在SOI晶片中以隔离晶片中的低电压和高电压元件。 隔离槽形成有不突出在沟槽上方的沟槽覆盖物。 形成垂直的沟槽内和水平的沟槽外隔离层，然后将沟槽填充到由隔离层形成的平面上方。 填充物被平坦化，并且去除位于沟槽内部的填充物的一部分。 然后去除一部分隔离层，并且去除填充物的一部分，使得填充物和沟槽中的隔离层处于大致相同的水平。 然后沉积覆盖层。 覆盖层在晶片的表面上方延伸到沟槽中，直到填充物和隔离层。 覆盖层另外平面化到大约顶部的沟槽。

公开(公告)号：US07517813B2

公开(公告)日：2009-04-14

申请号：US11576078

申请日：2005-10-06

Applicant: Ralf Lerner ,  Uwe Eckoldt

Inventor： Ralf Lerner ,  Uwe Eckoldt

IPC: H01L21/31 ,  H01L21/469

CPC classification number: H01L21/76202

Abstract: An efficient method for the thermal oxidation of preferably silicon semiconductor wafers using LOCOS (local oxidation of silicon) processes is described. The mechanical stresses of the wafers are to be reduced. To this end, an oxidation method is proposed that comprises providing a substrate (1) having a front side (12) to be patterned and a rear side (13). The substrate is oxidized in two steps. In a first step the rear side (13) is covered by a layer (4) that inhibits or hampers the oxidation. During a second step of the oxidation the oxidation-hampering layer (4) is no longer present. During both steps an oxide thickness is obtained on the front side (12) that is greater than an oxide thickness obtained on the rear side (13).

Abstract translation: 描述了使用LOCOS（硅的局部氧化）工艺优选硅半导体晶片的热氧化的有效方法。 要减小晶片的机械应力。 为此，提出了一种氧化方法，其包括提供具有待图案化的前侧（12）和后侧（13）的基板（1）。 基板被两步氧化。 在第一步骤中，后侧（13）被抑制或阻碍氧化的层（4）覆盖。 在氧化的第二步骤期间，氧化阻碍层（4）不再存在。 在两个步骤中，在前侧（12）上获得的氧化物厚度大于在后侧（13）获得的氧化物厚度。

公开(公告)号：US20090090992A1

公开(公告)日：2009-04-09

申请号：US12096661

申请日：2006-12-08

Applicant: Ralf Lerner ,  Uwe Eckoldt

Inventor： Ralf Lerner ,  Uwe Eckoldt

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76264 ,  H01L21/76224

Abstract: The invention relates to an isolation trench structure and a corresponding layout wherein the insulating properties of isolation trenches (10, 10′) in critical areas (at intersections and junctions) are improved. Flattened and/or rounded off corner areas (10a, 10b) of the semiconductor regions to be insulated are produced, the etching and filling behavior being adjusted to be similar to that in the areas outside the critical areas, a center island (18, 18′) being provided for adapting the effective trench width in the critical areas of transition. The isolation trench structure is suitable for semiconductor arrangements (smart power applications) in which large voltage differences occur between the regions (12, 12′) to be electrically insulated from each other and the corresponding components. Power components can be integrated on the same chip together with small-signal elements.

Abstract translation: 本发明涉及隔离沟槽结构和相应的布局，其中提高了临界区域（交叉点和结处）隔离沟槽（10,10'）的绝缘性能。 产生要被绝缘的半导体区域的平坦化和/或圆形角区域（10a，10b），将蚀刻和填充行为调整为与临界区域外的区域相似，中心岛（18,18 '）被提供用于适应转换关键区域中的有效沟槽宽度。 隔离沟槽结构适用于在彼此电绝缘的区域（12,12'）和相应的部件之间出现大的电压差的半导体布置（智能电力应用）。 电源组件可以与小信号元件一起集成在同一个芯片上。

公开(公告)号：US20080265364A1

公开(公告)日：2008-10-30

申请号：US10599726

申请日：2005-04-07

Applicant: Ralf Lerner ,  Uwe Eckoldt ,  Thomas Oetzel

Inventor： Ralf Lerner ,  Uwe Eckoldt ,  Thomas Oetzel

IPC: H01L21/762 ,  H01L27/12

CPC classification number: H01L21/76235

Abstract: The aim of the invention is to integrate low-voltage logic elements and high-voltage power elements in one and the same silicon circuit. Said aim is achieved by dielectrically chip regions having different potentials from each other with the aid of isolation trenches (10). In order to prevent voltage rises at sharp edges on the bottom of the isolation trenches, said edges are rounded in a simple process, part of the insulating layer (2) being isotropically etched.

Abstract translation: 本发明的目的是将低电压逻辑元件和高压功率元件集成在同一个硅电路中。 所述目的通过借助于隔离沟槽（10）彼此具有不同电位的介电芯片区域实现。 为了防止隔离沟底部的尖锐边缘处的电压上升，所述边缘以简单的工艺被倒圆，绝缘层（2）的一部分被各向同性地蚀刻。

公开(公告)号：US08722506B2

公开(公告)日：2014-05-13

申请号：US13139002

申请日：2009-12-23

Applicant: Steffen Reymann ,  Gerhard Fiehne ,  Uwe Eckoldt

Inventor： Steffen Reymann ,  Gerhard Fiehne ,  Uwe Eckoldt

IPC: H01L21/76

CPC classification number: G03F9/7084 ,  G03F9/7076 ,  G03F9/708 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to production of alignment marks on a semiconductor wafer with the use of a light-opaque layer (17), wherein, before the light-opaque layer (17) is applied, by means of the etching of cavities, free-standing pillar groups are produced in the cavities and then the light-opaque layer (17) is applied. The pillars are produced with a height of above 1 μm, which, moreover, is greater than a thickness of the light-opaque layer (17) to be applied in the cavities as layer portions (17x; 17y). The cavities are formed with a width such that they are filled only partly with the layer portions (17x; 17y) when the light-opaque layer (17) is applied. The high, freely positioned alignment marks produced by the method as pillar series (16x; 16y), having a plurality of individual pillars (16a; 16a′) in a cavity (12a, 12y), of a scribing trench on the semiconductor wafer are likewise described.

Abstract translation: 本发明涉及使用不透光层（17）在半导体晶片上制造对准标记，其中，在施加不透光层（17）之前，通过蚀刻空腔，独立地 在空腔中产生柱组，然后施加不透光层（17）。 产生高度大于1μm的柱，此外，其大于作为层部分（17x; 17y）施加在空腔中的不透光层（17）的厚度。 这些空腔形成为宽度，使得当应用不透光层（17）时，它们仅部分地填充有层部分（17x; 17y）。 在半导体晶片上的划线沟槽的空腔（12a，12y）中具有多个单独的支柱（16a，16a'）作为柱系列（16x; 16y）的方法产生的高自由定位的对准标记是 同样描述。

公开(公告)号：US07271074B2

公开(公告)日：2007-09-18

申请号：US10530343

申请日：2003-10-08

Applicant: Ralf Lerner ,  Uwe Eckoldt

Inventor： Ralf Lerner ,  Uwe Eckoldt

IPC: H01L21/762

CPC classification number: H01L21/76264 ,  H01L21/76283 ,  H01L21/76286

Abstract: Disclosed is a layer arrangement (4b, 5b, 9b, 10, 9a, 5a, 4a) within an insulating trench, which insulates circuits with little distortion while being suitable for electrically insulating high-voltage power components (7) relative to low-voltage logic elements (6) that are integrated on the same chip (1, 2, 3). Also disclosed is the production of a sequence of alternating vertical layers in a trench (T). The electric strength for high voltages is improved while the influence of defects created by distortions of substrate disks is prevented.

Abstract translation: 公开了一种在绝缘沟槽内的层布置（4b，5b，9b，10a，7a，5a，4a），其绝缘电路几乎没有变形，同时适用于电绝缘的高压功率部件 ）相对于集成在同一芯片（1,2,3）上的低电压逻辑元件（6）。 还公开了在沟槽（T）中产生交替的垂直层序列。 提高高电压的电强度，同时防止由基板盘的失真引起的缺陷的影响。

公开(公告)号：US5567284A

公开(公告)日：1996-10-22

申请号：US416676

申请日：1995-04-07

Applicant: Helmut Bauer ,  Foad Derisavi-Fard ,  Uwe Eckoldt ,  Ralf Gehrmann ,  Heribert Kickel

Inventor： Helmut Bauer ,  Foad Derisavi-Fard ,  Uwe Eckoldt ,  Ralf Gehrmann ,  Heribert Kickel

IPC: F03G7/00 ,  G05D23/19 ,  H01M10/34 ,  C25B9/00 ,  H01M8/18

CPC classification number: F03G7/005 ,  G05D23/1921 ,  H01M10/345

Abstract: An electrochemical actuator forms a sealed gas space inside of which there are a plurality of cells. Each cell has a solid electrode made from an electrochemically reversibly oxidizable material and a counter electrode. By applying a reversible direct current, an electrochemical reaction is initiated which results in a pressure increase or decrease in the gas space that can be used for generating movement. The manufacture of the actuator is simplified and manufacturing costs are lowered by providing a stackable spacer frame for each cell which is constructed of a material that is a relatively good heat conductor and an electric isolator. The rim of a metallic cell cup is attached to the spacer frame and a matrix soaked with an electrolyte is placed inside the cup. Each cell further has a solid electrode, a separator and a counter electrode which, together with the spacer frame, are assembled into a cell. When the cells are stacked, the counter electrode of each cell is placed against the cell cup of the adjoining cell.

Abstract translation: PCT No.PCT / EP94 / 02289第 371日期：1995年4月7日 102（e）1995年4月7日PCT PCT 1994年7月7日PCT公布。 公开号WO95 / 08709 日期1995年3月30日电化学致动器形成密封的气体空间，其内有多个电池。 每个电池具有由电化学可逆地氧化的材料和对电极制成的固体电极。 通过施加可逆直流电流，开始电化学反应，这导致可用于产生运动的气体空间中的压力增加或减小。 致动器的制造被简化，并且通过为由相对较好的导热体和电隔离器的材料构成的每个电池提供可堆叠的间隔框架来降低制造成本。 金属电池杯的边缘连接到间隔框架，并且用电解质浸泡的基体放置在杯内。 每个电池还具有固体电极，隔板和对电极，与间隔框架一起组装成电池。 当电池堆叠时，每个电池的对电极被放置在邻接的电池的电池杯上。

公开(公告)号：US20120098084A1

公开(公告)日：2012-04-26

申请号：US12999658

申请日：2009-06-19

Applicant: Ralf Lerner ,  Uwe Eckoldt

Inventor： Ralf Lerner ,  Uwe Eckoldt

IPC: H01L29/06 ,  H01L21/762

CPC classification number: H01L21/76224 ,  H01L21/76264

Abstract: A semiconductor component with straight insulation trenches formed in a semiconductor material providing semiconductor areas laterally insulated from each other. Each insulation trench has a uniform width along its longitudinal direction represented by a central line. The semiconductor component has an intersecting area into which at least three of the straight insulation trenches lead. A center of the intersecting area is defined as a point of intersection of the continuations of the center lines. A central semiconductor area disposed in the intersecting area is connected with one of the semiconductor areas and contains the center of the intersecting area.

Abstract translation: 一种半导体元件，其具有形成在半导体材料中的直的绝缘沟槽，从而提供横向绝缘的半导体区域。 每个绝缘沟槽沿着由中心线表示的纵向方向具有均匀的宽度。 半导体部件具有交叉区域，至少三个直的绝缘沟槽引导到该相交区域。 相交区域的中心被定义为中心线的连续点的交点。 设置在交叉区域的中央半导体区域与半导体区域中的一个连接并且包含交叉区域的中心。

公开(公告)号：US20120032356A1

公开(公告)日：2012-02-09

申请号：US13139002

申请日：2009-12-23

Applicant: Steffen Reymann ,  Gerhard Fiehne ,  Uwe Eckoldt

Inventor： Steffen Reymann ,  Gerhard Fiehne ,  Uwe Eckoldt

IPC: H01L23/544 ,  H01L21/02

CPC classification number: G03F9/7084 ,  G03F9/7076 ,  G03F9/708 ,  H01L23/544 ,  H01L2223/54426 ,  H01L2223/5446 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The invention relates to production of alignment marks on a semiconductor wafer with the use of a light-opaque layer (17), wherein, before the light-opaque layer (17) is applied, by means of the etching of cavities, free-standing pillar groups are produced in the cavities and then the light-opaque layer (17) is applied. The pillars are produced with a height of above 1 μm, which, moreover, is greater than a thickness of the light-opaque layer (17) to be applied in the cavities as layer portions (17x; 17y). The cavities are formed with a width such that they are filled only partly with the layer portions (17x; 17y) when the light-opaque layer (17) is applied. The high, freely positioned alignment marks produced by the method as pillar series (16x; 16y), having a plurality of individual pillars (16a; 16a′) in a cavity (12a, 12y), of a scribing trench on the semiconductor wafer are likewise described.

Abstract translation: 本发明涉及使用不透光层（17）在半导体晶片上制造对准标记，其中，在施加不透光层（17）之前，通过蚀刻空腔，独立地 在空腔中产生柱组，然后施加不透光层（17）。 产生高度大于1μm的柱，此外，其大于作为层部分（17x; 17y）施加在空腔中的不透光层（17）的厚度。 这些空腔形成为宽度，使得当应用不透光层（17）时，它们仅部分地填充有层部分（17x; 17y）。 在半导体晶片上的划线沟槽的空腔（12a，12y）中具有多个单独的支柱（16a，16a'）作为柱系列（16x; 16y）的方法产生的高自由定位的对准标记是 同样描述。