SYSTEM AND METHOD FOR ATOMICALLY UPDATING SHARED MEMORY IN MULTIPROCESSOR SYSTEM
    1.
    发明申请
    SYSTEM AND METHOD FOR ATOMICALLY UPDATING SHARED MEMORY IN MULTIPROCESSOR SYSTEM 审中-公开
    用于在多处理器系统中原形更新共享存储器的系统和方法

    公开(公告)号:US20150012711A1

    公开(公告)日:2015-01-08

    申请号:US13935550

    申请日:2013-07-04

    IPC分类号: G06F12/08

    CPC分类号: G06F12/084

    摘要: A system for operating a shared memory of a multiprocessor system includes a set of processor cores and a corresponding set of core local caches, a set of I/O devices and a corresponding set of I/O device local caches. Read and write operations performed on a core local cache, an I/O device local cache, and the shared memory are governed by a cache coherence protocol (CCP) that ensures that the shared memory is updated atomically.

    摘要翻译: 用于操作多处理器系统的共享存储器的系统包括一组处理器核心和相应的一组核心本地高速缓存,一组I / O设备和相应的一组I / O设备本地高速缓存。 在本地高速缓存,I / O设备本地缓存和共享存储器上执行的读写操作由缓存一致性协议(CCP)来管理,该协议确保共享存储器以原子方式更新。

    MULTI-CORE PROCESSOR FOR MANAGING DATA PACKETS IN COMMUNICATION NETWORK
    2.
    发明申请
    MULTI-CORE PROCESSOR FOR MANAGING DATA PACKETS IN COMMUNICATION NETWORK 有权
    用于管理通信网络中的数据包的多核处理器

    公开(公告)号:US20150301975A1

    公开(公告)日:2015-10-22

    申请号:US14258046

    申请日:2014-04-22

    IPC分类号: G06F13/42 G06F13/40 G06F13/24

    摘要: A system for managing data packets has multiple cores, a data buffer, a hardware accelerator, and an interrupt controller. The interrupt controller transmits a first interrupt signal to a first one of the cores based on a first hardware signal received from the hardware accelerator. The first core creates a copy of buffer descriptors (BD) of a buffer descriptor ring that correspond to the data packets in the data buffer in a first virtual queue and indicates to the hardware accelerator that the data packets are processed. If there are additional data packets, the interrupt controller transmits a second interrupt signal to a second core, which performs the same steps as performed by the first core. The first and the second cores simultaneously process the data packets associated with the BDs in the first and second virtual queues, respectively.

    摘要翻译: 用于管理数据包的系统具有多个核心,数据缓冲器,硬件加​​速器和中断控制器。 中断控制器基于从硬件加速器接收到的第一硬件信号将第一中断信号发送到第一核心。 第一核心创建与第一虚拟队列中的数据缓冲器中的数据分组相对应的缓冲器描述符环的缓冲器描述符(BD)的副本,并向硬件加速器指示数据分组被处理。 如果存在额外的数据分组,则中断控制器将第二中断信号发送到第二核心,其执行与由第一核心执行的步骤相同的步骤。 第一和第二核心分别同时处理与第一和第二虚拟队列中的BD相关联的数据分组。

    System for pre-fetching data frames using hints from work queue scheduler

    公开(公告)号:US09606926B2

    公开(公告)日:2017-03-28

    申请号:US14556143

    申请日:2014-11-29

    IPC分类号: G06F12/00 G06F12/0862

    摘要: A system for pre-fetching a data frame from a system memory to a cache memory includes a processor, a queue manager, and a pre-fetch manager. The processor issues a de-queue request associated with the data frame. The queue manager receives the de-queue request, identifies a frame descriptor associated with the data frame, and generates a pre-fetch hint signal. The pre-fetch manager receives the pre-fetch hint signal and generates a pre-fetch signal and enables the cache memory to pre-fetch the data frame. Subsequently, the queue manager de-queues the frame descriptor. The processor receives the frame descriptor and reads the data frame from the cache memory.

    SYSTEM FOR PRE-FETCHING DATA FRAMES USING HINTS FROM WORK QUEUE SCHEDULER
    4.
    发明申请
    SYSTEM FOR PRE-FETCHING DATA FRAMES USING HINTS FROM WORK QUEUE SCHEDULER 有权
    用于使用工作队列调度员的提示来预先切断数据框架的系统

    公开(公告)号:US20160154737A1

    公开(公告)日:2016-06-02

    申请号:US14556143

    申请日:2014-11-29

    IPC分类号: G06F12/08

    摘要: A system for pre-fetching a data frame from a system memory to a cache memory includes a processor, a queue manager, and a pre-fetch manager. The processor issues a de-queue request associated with the data frame. The queue manager receives the de-queue request, identifies a frame descriptor associated with the data frame, and generates a pre-fetch hint signal. The pre-fetch manager receives the pre-fetch hint signal and generates a pre-fetch signal and enables the cache memory to pre-fetch the data frame. Subsequently, the queue manager de-queues the frame descriptor. The processor receives the frame descriptor and reads the data frame from the cache memory.

    摘要翻译: 用于将数据帧从系统存储器预取入高速缓冲存储器的系统包括处理器,队列管理器和预取管理器。 处理器发出与数据帧相关联的解除队列请求。 队列管理器接收去队列请求,识别与数据帧相关联的帧描述符,并生成预取提示信号。 预取管理器接收预取提示信号并产生预取信号,并使缓存存储器能够预取数据帧。 随后,队列管理器对帧描述符进行排队。 处理器接收帧描述符并从高速缓冲存储器读取数据帧。

    MULTI-CORE SYSTEM FOR PROCESSING DATA PACKETS
    5.
    发明申请
    MULTI-CORE SYSTEM FOR PROCESSING DATA PACKETS 有权
    用于处理数据包的多核系统

    公开(公告)号:US20160274936A1

    公开(公告)日:2016-09-22

    申请号:US14660905

    申请日:2015-03-17

    IPC分类号: G06F9/48 G06F9/46

    CPC分类号: G06F9/4881 G06F9/466 G06F9/52

    摘要: A data processing system includes a host processor, a co-processor, and a memory that includes multiple buffer descriptor (BD) rings. The host processor includes multiple cores that execute multiple threads to process data packets stored in the memory. The host processor generates a notification command based on multiple context switch events that occur in the cores. The notification command indicates a context switch event type and BD ring IDs associated with BD rings to be polled by the co-processor. The BD rings are referred to as active BD rings. The co-processor polls only the active BD rings based on the notification command and processes the data packets associated with the active BD rings.

    摘要翻译: 数据处理系统包括主处理器,协处理器和包括多个缓冲器描述符(BD)环的存储器。 主处理器包括执行多个线程以处理存储在存储器中的数据分组的多个核。 主机处理器基于核心中发生的多个上下文切换事件来生成通知命令。 通知命令指示与协处理器轮询的BD环相关联的上下文切换事件类型和BD环ID。 BD环被称为活动BD环。 协处理器仅基于通知命令轮询主动BD环,并处理与活动BD环相关联的数据包。

    Multi-core processor for managing data packets in communication network
    6.
    发明授权
    Multi-core processor for managing data packets in communication network 有权
    用于管理通信网络中数据包的多核处理器

    公开(公告)号:US09396154B2

    公开(公告)日:2016-07-19

    申请号:US14258046

    申请日:2014-04-22

    摘要: A system for managing data packets has multiple cores, a data buffer, a hardware accelerator, and an interrupt controller. The interrupt controller transmits a first interrupt signal to a first one of the cores based on a first hardware signal received from the hardware accelerator. The first core creates a copy of buffer descriptors (BD) of a buffer descriptor ring that correspond to the data packets in the data buffer in a first virtual queue and indicates to the hardware accelerator that the data packets are processed. If there are additional data packets, the interrupt controller transmits a second interrupt signal to a second core, which performs the same steps as performed by the first core. The first and the second cores simultaneously process the data packets associated with the BDs in the first and second virtual queues, respectively.

    摘要翻译: 用于管理数据包的系统具有多个核心,数据缓冲器,硬件加​​速器和中断控制器。 中断控制器基于从硬件加速器接收到的第一硬件信号将第一中断信号发送到第一核心。 第一核心创建与第一虚拟队列中的数据缓冲器中的数据分组相对应的缓冲器描述符环的缓冲器描述符(BD)的副本,并向硬件加速器指示数据分组被处理。 如果存在额外的数据分组,则中断控制器将第二中断信号发送到第二核心,其执行与由第一核心执行的步骤相同的步骤。 第一和第二核心分别同时处理与第一和第二虚拟队列中的BD相关联的数据分组。

    Multi-core system for processing data packets
    7.
    发明授权
    Multi-core system for processing data packets 有权
    用于处理数据包的多核系统

    公开(公告)号:US09569264B2

    公开(公告)日:2017-02-14

    申请号:US14660905

    申请日:2015-03-17

    IPC分类号: G06F9/48 G06F9/46 G06F9/52

    CPC分类号: G06F9/4881 G06F9/466 G06F9/52

    摘要: A data processing system includes a host processor, a co-processor, and a memory that includes multiple buffer descriptor (BD) rings. The host processor includes multiple cores that execute multiple threads to process data packets stored in the memory. The host processor generates a notification command based on multiple context switch events that occur in the cores. The notification command indicates a context switch event type and BD ring IDs associated with BD rings to be polled by the co-processor. The BD rings are referred to as active BD rings. The co-processor polls only the active BD rings based on the notification command and processes the data packets associated with the active BD rings.

    摘要翻译: 数据处理系统包括主处理器,协处理器和包括多个缓冲器描述符(BD)环的存储器。 主处理器包括执行多个线程以处理存储在存储器中的数据分组的多个核。 主机处理器基于核心中发生的多个上下文切换事件来生成通知命令。 通知命令指示与协处理器轮询的BD环相关联的上下文切换事件类型和BD环ID。 BD环被称为活动BD环。 协处理器仅基于通知命令轮询主动BD环,并处理与活动BD环相关联的数据包。

    System and method for dynamically migrating stash transactions
    8.
    发明授权
    System and method for dynamically migrating stash transactions 有权
    动态迁移隐藏事务的系统和方法

    公开(公告)号:US08671232B1

    公开(公告)日:2014-03-11

    申请号:US13789661

    申请日:2013-03-07

    IPC分类号: G06F3/00 G06F13/14

    CPC分类号: G06F12/1081 G06F13/28

    摘要: A system and method for dynamically migrating stash transactions include first and second processing cores, an input/output memory management unit (IOMMU), an IOMMU mapping table, an input/output (I/O) device, a stash transaction migration management unit (STMMU), and an operating system (OS) scheduler. The first core executes a first thread associated with a frame manager. The OS scheduler migrates the first thread from the first core to the second core and generates pre-empt notifiers to indicate scheduling-out and scheduling-in of the first thread from the first core and to the second core. The STMMU uses the pre-empt notifiers to enable dynamic stash transaction migration.

    摘要翻译: 用于动态迁移存储交易的系统和方法包括第一和第二处理核心,输入/输出存储器管理单元(IOMMU),IOMMU映射表,输入/输出(I / O)设备,存储交易迁移管理单元 STMMU)和操作系统(OS)调度程序。 第一个核心执行与帧管理器相关联的第一个线程。 OS调度程序将第一个线程从第一个核心迁移到第二个核心,并生成预先通过的通知程序,以指示第一个线程从第一个核心到第二个核心的排除和调度。 STMMU使用先进的通知器来启用动态隐藏事务迁移。

    INTER-PARTITION COMMUNICATION IN MULTI-CORE PROCESSOR
    9.
    发明申请
    INTER-PARTITION COMMUNICATION IN MULTI-CORE PROCESSOR 审中-公开
    多核处理器中的分段通信

    公开(公告)号:US20130227243A1

    公开(公告)日:2013-08-29

    申请号:US13403964

    申请日:2012-02-23

    申请人: Vakul Garg

    发明人: Vakul Garg

    IPC分类号: G06F12/02

    CPC分类号: G06F9/544 G06F12/0284

    摘要: A multi-core processor includes logical partitions that have respective processor cores, memory areas, and Ethernet controllers. At least one of the Ethernet controllers is disabled for external communication and is assigned as an inter-partition Ethernet controller for inter-partition communication. The inter-partition Ethernet controller is configured in loopback mode. A transmitting partition addresses a message through a send buffer in a private memory area to the inter-partition Ethernet controller assigned to a receiving partition. The receiving inter-partition Ethernet controller copies the received message to a receive buffer in the receiving partition's memory area. The receive Ethernet controller returns the received message to the sending partition and the sending partition resumes control of the memory space of the send buffer, or alternatively, the receive Ethernet controller frees the memory space of the send buffer to the private memory of the sending partition.

    摘要翻译: 多核处理器包括具有相应处理器核心,存储区域和以太网控制器的逻辑分区。 至少有一个以太网控制器禁用外部通信,并被分配为分区间以太网控制器进行分区间通信。 分区间以太网控制器配置为环回模式。 发送分区通过专用存储器区域中的发送缓冲区将消息分配给分配给接收分区的分区间以太网控制器。 接收分区间以太网控制器将接收到的消息复制到接收分区的存储区域中的接收缓冲区。 接收以太网控制器将接收到的消息返回给发送分区,发送分区恢复对发送缓冲区的存储空间的控制,或者接收以太网控制器将发送缓冲区的存储空间释放到发送分区的专用存储器 。