公开(公告)号：US20120306569A1

公开(公告)日：2012-12-06

申请号：US13490110

申请日：2012-06-06

Applicant: Eric Nestler ,  Jeffrey Venuti ,  Vladimir Zlatkovic ,  Kartik Nanda

Inventor： Eric Nestler ,  Jeffrey Venuti ,  Vladimir Zlatkovic ,  Kartik Nanda

IPC: H03K5/00

CPC classification number: H03K5/00 ,  H03H15/02

Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.

Abstract translation: 时域滤波方法采用无源电荷共享方式来实现无限脉冲响应滤波器。 将输入信号的延迟样本作为电荷存储在第一电容器阵列的电容器上，并且输出信号的延迟采样作为电荷存储在第二电容器阵列的电容器上。 输出由第一和第二阵列的电容器彼此无源耦合确定，并根据耦合的电容器上的总电荷来确定输出。 在一些示例中，在将输出存储在第二电容器阵列之前，将增益应用于总电荷。 在一些示例中，在耦合电容器之前，将电荷量化电路应用于存储在阵列上的电荷以形成输出。

公开(公告)号：US08188753B2

公开(公告)日：2012-05-29

申请号：US12545590

申请日：2009-08-21

Applicant: Eric Nestler ,  Vladimir Zlatkovic

Inventor： Eric Nestler ,  Vladimir Zlatkovic

IPC: G01R27/26

CPC classification number: H03H15/02 ,  G01D5/24 ,  G01R27/2605 ,  G01R31/028 ,  G06F17/14 ,  G06G7/19

Abstract: Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.

Abstract translation: 本发明的一些一般方面涉及电路和模拟计算的方法，例如使用开关电容器集成电路。 在一些示例中，电路包括第一组电容器和可在电路操作期间存储电荷的第二组电容器。 第一和/或第二组电容器可以包括电容器的多个不相交的子集。 提供输入电路，用于根据相应的输入信号接收一组输入信号并用于在第一组电容器中的一些或全部电容器的每一个上感应电荷。 开关，例如，由一系列时钟信号控制的晶体管，用于耦合不同组的电容器。 开关的不同配置用于形成不同的电容器组，其中电荷可重新分布。

公开(公告)号：US09036420B2

公开(公告)日：2015-05-19

申请号：US13471816

申请日：2012-05-15

Applicant: Benjamin Vigoda ,  Jeffrey Bernstein ,  Jeffrey Venuti ,  Alexander Alexeyev ,  Eric Nestler ,  David Reynolds ,  William Bradley ,  Vladimir Zlatkovic

Inventor： Benjamin Vigoda ,  Jeffrey Bernstein ,  Jeffrey Venuti ,  Alexander Alexeyev ,  Eric Nestler ,  David Reynolds ,  William Bradley ,  Vladimir Zlatkovic

IPC: G11C16/04 ,  G11C7/00 ,  G11C7/10 ,  G11C7/16 ,  G11C11/56 ,  G11C27/00 ,  G11C11/24 ,  G11C29/00

CPC classification number: G11C7/00 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/24 ,  G11C11/5642 ,  G11C16/04 ,  G11C27/005 ,  G11C29/00

Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

Abstract translation: 存储装置包括具有一组存储元件的存储阵列。 每个存储元件可以写入一组离散的物理状态。 读取电路选择一个或多个存储元件，并为每个选定的存储元件生成表示所选存储元件的物理状态的模拟信号。 信号处理电路处理模拟信号以产生多个输出，其中每个输出表示所选择的存储元件与离散的物理状态集合中的一个或多个的不同子集的关联程度。

公开(公告)号：US08717094B2

公开(公告)日：2014-05-06

申请号：US13490110

申请日：2012-06-06

Applicant: Eric Nestler ,  Jeffrey Venuti ,  Vladimir Zlatkovic ,  Kartik Nanda

Inventor： Eric Nestler ,  Jeffrey Venuti ,  Vladimir Zlatkovic ,  Kartik Nanda

IPC: H03K5/00

CPC classification number: H03K5/00 ,  H03H15/02

Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.

Abstract translation: 时域滤波方法采用无源电荷共享方式来实现无限脉冲响应滤波器。 将输入信号的延迟样本作为电荷存储在第一电容器阵列的电容器上，并且输出信号的延迟采样作为电荷存储在第二电容器阵列的电容器上。 输出由第一和第二阵列的电容器彼此无源耦合确定，并根据耦合的电容器上的总电荷来确定输出。 在一些示例中，在将输出存储在第二电容器阵列之前，将增益应用于总电荷。 在一些示例中，在耦合电容器之前，将电荷量化电路应用于存储在阵列上的电荷以形成输出。

公开(公告)号：US08547272B2

公开(公告)日：2013-10-01

申请号：US13813101

申请日：2011-08-18

Applicant: Eric Nestler ,  Vladimir Zlatkovic ,  Jeffrey Venuti

Inventor： Eric Nestler ,  Vladimir Zlatkovic ,  Jeffrey Venuti

IPC: H03M1/12

CPC classification number: H03H7/0138 ,  G06F17/5063 ,  G10K15/00 ,  H02M1/14 ,  H03H15/00 ,  H03H15/02 ,  H03M1/12 ,  H04R25/00

Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.

Abstract translation: 在一个方面，离散时间模拟信号处理模块的降低的功耗和/或电路面积是通过使用完全或很大程度上被动电荷共享电路的方法实现的，其中可能包括可配置（例如，在制造之后，在 运行时）乘法缩放阶段，不需要信号路径中的有源设备。 在一些示例中，乘法系数被数字地表示，并且被变换以配置可重构电路以实现期望系数和电荷转移程度之间的线性关系。 在一些示例中，使用多个连续的电荷共享阶段来实现期望的乘法效应，其提供大的动态范围的系数，而不需要电容元件尺寸的相应范围。 缩放电路可以组合以形成可配置的时域或频域滤波器。

公开(公告)号：US20130207827A1

公开(公告)日：2013-08-15

申请号：US13813101

申请日：2011-08-18

Applicant: Eric Nestler ,  Vladimir Zlatkovic ,  Jeffrey Venuti

Inventor： Eric Nestler ,  Vladimir Zlatkovic ,  Jeffrey Venuti

IPC: H03H15/00 ,  H03M1/12

CPC classification number: H03H7/0138 ,  G06F17/5063 ,  G10K15/00 ,  H02M1/14 ,  H03H15/00 ,  H03H15/02 ,  H03M1/12 ,  H04R25/00

Abstract: In one aspect, reduced power consumption and/or circuit area of a discrete time analog signal processing module is achieved in an approach that makes use of entirely, or largely, passive charge sharing circuitry, which may include configurable (e.g., after fabrication, at runtime) multiplicative scaling stages that do not require active devices in the signal path. In some examples, multiplicative coefficients are represented digitally, and are transformed to configure the reconfigurable circuitry to achieve a linear relationship between a desired coefficient and a degree of charge transfer. In some examples, multiple successive charge sharing phases are used to achieve a desired multiplicative effect that provides a large dynamic range of coefficients without requiring a commensurate range of sizes of capacitive elements. The scaling circuits can be combined to form configurable time domain or frequency domain filters.

Abstract translation: 在一个方面，离散时间模拟信号处理模块的降低的功耗和/或电路面积是通过使用完全或很大程度上被动电荷共享电路的方法实现的，其中可能包括可配置（例如，在制造之后，在 运行时）乘法缩放阶段，不需要信号路径中的有源设备。 在一些示例中，乘法系数被数字地表示，并且被变换以配置可重构电路以实现期望系数和电荷转移程度之间的线性关系。 在一些示例中，使用多个连续的电荷共享阶段来实现期望的乘法效应，其提供大的动态范围的系数，而不需要电容元件尺寸的相应范围。 缩放电路可以组合以形成可配置的时域或频域滤波器。

公开(公告)号：US20130080497A1

公开(公告)日：2013-03-28

申请号：US13482112

申请日：2012-05-29

Applicant: Eric Nestler ,  Vladimir Zlatkovic

Inventor： Eric Nestler ,  Vladimir Zlatkovic

IPC: G06F17/14

CPC classification number: H03H15/02 ,  G01D5/24 ,  G01R27/2605 ,  G01R31/028 ,  G06F17/14 ,  G06G7/19

Abstract: Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.

Abstract translation: 本发明的一些一般方面涉及电路和模拟计算的方法，例如使用开关电容器集成电路。 在一些示例中，电路包括第一组电容器和可在电路操作期间存储电荷的第二组电容器。 第一和/或第二组电容器可以包括电容器的多个不相交的子集。 提供输入电路，用于根据相应的输入信号接收一组输入信号并用于在第一组电容器中的一些或全部电容器的每一个上感应电荷。 开关，例如，由一系列时钟信号控制的晶体管，用于耦合不同组的电容器。 开关的不同配置用于形成不同的电容器组，其中电荷可重新分布。

公开(公告)号：US09218318B2

公开(公告)日：2015-12-22

申请号：US13482112

申请日：2012-05-29

Applicant: Eric Nestler ,  Vladimir Zlatkovic

Inventor： Eric Nestler ,  Vladimir Zlatkovic

IPC: G01R27/26 ,  G06F17/14 ,  G06G7/19 ,  G01D5/24 ,  G01R31/02

CPC classification number: H03H15/02 ,  G01D5/24 ,  G01R27/2605 ,  G01R31/028 ,  G06F17/14 ,  G06G7/19

Abstract: Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.

Abstract translation: 本发明的一些一般方面涉及电路和模拟计算的方法，例如使用开关电容器集成电路。 在一些示例中，电路包括第一组电容器和可在电路操作期间存储电荷的第二组电容器。 第一和/或第二组电容器可以包括电容器的多个不相交的子集。 提供输入电路，用于根据相应的输入信号接收一组输入信号并用于在第一组电容器中的一些或全部电容器的每一个上感应电荷。 开关，例如，由一系列时钟信号控制的晶体管，用于耦合不同组的电容器。 开关的不同配置用于形成不同的电容器组，其中电荷可重新分布。

公开(公告)号：US08179731B2

公开(公告)日：2012-05-15

申请号：US12537045

申请日：2009-08-06

Applicant: Benjamin Vigoda ,  Eric Nestler ,  Jeffrey Bernstein ,  David Reynolds ,  Alexander Alexeyev ,  Jeffrey Venuti ,  William Bradley ,  Vladimir Zlatkovic

Inventor： Benjamin Vigoda ,  Eric Nestler ,  Jeffrey Bernstein ,  David Reynolds ,  Alexander Alexeyev ,  Jeffrey Venuti ,  William Bradley ,  Vladimir Zlatkovic

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/24 ,  G11C11/5642 ,  G11C16/04 ,  G11C27/005 ,  G11C29/00

Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

公开(公告)号：US08107306B2

公开(公告)日：2012-01-31

申请号：US12537081

申请日：2009-08-06

Applicant: Benjamin Vigoda ,  Eric Nestler ,  Jeffrey Bernstein ,  David Reynolds ,  Alexander Alexeyev ,  Jeffrey Venuti ,  William Bradley ,  Vladimir Zlatkovic

Inventor： Benjamin Vigoda ,  Eric Nestler ,  Jeffrey Bernstein ,  David Reynolds ,  Alexander Alexeyev ,  Jeffrey Venuti ,  William Bradley ,  Vladimir Zlatkovic

IPC: G11C7/00

CPC classification number: G11C7/00 ,  G11C7/1006 ,  G11C7/16 ,  G11C11/24 ,  G11C11/5642 ,  G11C16/04 ,  G11C27/005 ,  G11C29/00

Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

Abstract translation: 存储装置包括具有一组存储元件的存储阵列。 每个存储元件可以写入一组离散的物理状态。 读取电路选择一个或多个存储元件，并为每个选定的存储元件生成表示所选存储元件的物理状态的模拟信号。 信号处理电路处理模拟信号以产生多个输出，其中每个输出表示所选择的存储元件与离散的物理状态集合中的一个或多个的不同子集的关联程度。