Method and system for selecting implementation of a filter controller between a single conversion mode that ensures a fully-settled converted output and a continuous conversion mode
    1.
    发明授权
    Method and system for selecting implementation of a filter controller between a single conversion mode that ensures a fully-settled converted output and a continuous conversion mode 有权
    用于在确保完全转换的输出和连续转换模式的单个转换模式之间选择滤波器控制器的实现的方法和系统

    公开(公告)号:US06469650B2

    公开(公告)日:2002-10-22

    申请号:US09800604

    申请日:2001-03-06

    IPC分类号: H03M112

    CPC分类号: H03M3/392 H03M3/474

    摘要: A method and system for selecting implementation of a filter controller between a single conversion that ensures a fully-settled converted output and a continuous conversion of an input signal are disclosed. State machine determines whether convert start signal has a duration, which ends on or before a first occurrence of a conversion done on the input signal. Conversion done is an occurrence of when a bit set has been converted from the input signal. If convert start signal has a duration which ends on or before the first occurrence of conversion done, then state machine selects and implements single conversion of the input signal. Digital system ensures a fully-settled converted output by waiting for the filter to receive and filter a predetermined number of bit sets for a conversion output and then outputting the conversion output. Otherwise, state machine selects and implements continuous conversion of the input signal.

    摘要翻译: 公开了一种用于在确保完全稳定的转换输出和输入信号的连续转换的单个转换之间选择滤波器控制器的实现的方法和系统。 状态机确定转换开始信号是否具有持续时间,其结束于在输入信号上完成的转换的第一次出现之后或之前。 完成的转换是当从输入信号转换位设置时的出现。 如果转换开始信号具有在第一次完成转换之前或之前结束的持续时间,则状态机选择并实现输入信号的单次转换。 数字系统通过等待滤波器接收和过滤用于转换输出的预定数量的位组,然后输出转换输出,确保完全转换的输出。 否则,状态机选择并实现输入信号的连续转换。

    SYSTEM AND METHOD FOR MANAGING THE DELIVERY OF ELECTRIC POWER
    2.
    发明申请
    SYSTEM AND METHOD FOR MANAGING THE DELIVERY OF ELECTRIC POWER 审中-公开
    用于管理电力输送的系统和方法

    公开(公告)号:US20170012429A1

    公开(公告)日:2017-01-12

    申请号:US15202659

    申请日:2016-07-06

    申请人: Kartik Nanda

    发明人: Kartik Nanda

    IPC分类号: H02J3/38

    摘要: A system for managing delivery of electric power includes at least one source of electric power supplying an aggregate amount of available power and a plurality of electrical loads, each having a priority designation. There is a power management system electrically connected to the source of electrical power and to the plurality of electrical loads. The power management system monitors electrical power demanded by the electrical loads and the aggregate amount of available power of the at least one source of electric power. When the power management system determines that the aggregate demanded power exceeds the aggregate amount of available power, the power management system continues to provide power to each of said electrical loads but at a power level which is less than demanded to one or more of said plurality of electrical loads based on the priority designation of each of said electrical loads.

    摘要翻译: 用于管理电力输送的系统包括提供总量的可用功率和多个电负载的至少一个电源,每个电负载源具有优先级指定。 电源管理系统电连接到电源和多个电负载。 电力管理系统监视由电力负载所需的电力和至少一个电力来源的可用功率的总量。 当电力管理系统确定总需求功率超过可用功率的总量时,电力管理系统继续向每个所述电负载提供功率,但是功率水平小于所要求的一个或多个所述多个电力 基于每个所述电负载的优先级指定的电负载。

    Charge sharing time domain filter
    3.
    发明授权
    Charge sharing time domain filter 有权
    电荷共享时域滤波器

    公开(公告)号:US08717094B2

    公开(公告)日:2014-05-06

    申请号:US13490110

    申请日:2012-06-06

    IPC分类号: H03K5/00

    CPC分类号: H03K5/00 H03H15/02

    摘要: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.

    摘要翻译: 时域滤波方法采用无源电荷共享方式来实现无限脉冲响应滤波器。 将输入信号的延迟样本作为电荷存储在第一电容器阵列的电容器上,并且输出信号的延迟采样作为电荷存储在第二电容器阵列的电容器上。 输出由第一和第二阵列的电容器彼此无源耦合确定,并根据耦合的电容器上的总电荷来确定输出。 在一些示例中,在将输出存储在第二电容器阵列之前,将增益应用于总电荷。 在一些示例中,在耦合电容器之前,将电荷量化电路应用于存储在阵列上的电荷以形成输出。

    Circuits and methods for implementing mode selection in multiple-mode integrated circuits
    4.
    发明授权
    Circuits and methods for implementing mode selection in multiple-mode integrated circuits 有权
    用于在多模集成电路中实现模式选择的电路和方法

    公开(公告)号:US07605723B2

    公开(公告)日:2009-10-20

    申请号:US11011983

    申请日:2004-12-14

    IPC分类号: H03M7/00

    CPC分类号: G06F1/22 H03M3/396 H03M3/50

    摘要: Mode selection circuitry selects one of a plurality of operational modes supported by an integrated circuit by detecting a selected connection between a first terminal of the integrated circuit and a mode control terminal of the integrated circuit. Other including a mode control terminal coupled to an integrated circuit for receiving a mode selection signal and mode select circuitry for selecting an operational mode of the integrated circuit in response to a frequency of the mode control signal.

    摘要翻译: 模式选择电路通过检测集成电路的第一端和集成电路的模式控制端之间的所选连接来选择由集成电路支持的多种操作模式之一。 其他包括耦合到用于接收模式选择信号的集成电路的模式控制终端和用于响应于模式控制信号的频率来选择集成电路的操作模式的模式选择电路。

    SWITCH STATE CONTROLLER WITH A SENSE CURRENT GENERATED OPERATING VOLTAGE
    5.
    发明申请
    SWITCH STATE CONTROLLER WITH A SENSE CURRENT GENERATED OPERATING VOLTAGE 有权
    开关状态控制器,具有感应电流产生的工作电压

    公开(公告)号:US20090189579A1

    公开(公告)日:2009-07-30

    申请号:US12165556

    申请日:2008-06-30

    IPC分类号: H02M3/156

    摘要: A power supply system and method includes a switch state controller that is operational to control a switching power converter during certain power loss conditions that cause conventional switch state controllers to have diminished or no functionality. In at least one embodiment, during certain power loss conditions, such as when an auxiliary power supply is in standby mode or when the switching power converter is not operating, a power supply for the switch state controller does not provide sufficient operating power to the switch state controller during certain power loss conditions. In at least one embodiment, during such power loss conditions power is generated for the switch state controller using sense input and/or sense output currents of the switching power converter to allow an integrated circuit (IC) switch state controller to generate a control signal to control a switch of the switching power converter.

    摘要翻译: 电源系统和方法包括开关状态控制器,该开关状态控制器在导致常规开关状态控制器已经减小或没有功能的某些功率损耗条件下可操作以控制开关功率转换器。 在至少一个实施例中,在某些功率损耗状态下,例如当辅助电源处于待机模式时或者当开关电源转换器不工作时,开关状态控制器的电源不能向开关提供足够的工作电力 在某些功率损耗条件下状态控制器。 在至少一个实施例中,在这种功率损耗状态期间,使用开关功率转换器的感测输入和/或感测输出电流为开关状态控制器产生功率,以允许集成电路(IC)开关状态控制器产生控制信号 控制开关电源转换器的开关。

    TEMPERATURE AND PROCESS-STABLE MAGNETIC FIELD SENSOR BIAS CURRENT SOURCE
    6.
    发明申请
    TEMPERATURE AND PROCESS-STABLE MAGNETIC FIELD SENSOR BIAS CURRENT SOURCE 有权
    温度和过程稳定磁场传感器偏置电流源

    公开(公告)号:US20090160535A1

    公开(公告)日:2009-06-25

    申请号:US11962022

    申请日:2007-12-20

    IPC分类号: G05F3/02

    摘要: A temperature and process-stable magnetic field sensor bias current source provides improved performance in Hall effect sensor circuits. A switched-capacitor sensing element is used to sense either a reference current or the bias current directly. A current mirror may be used to generate the bias current from the reference current, and may include multiple current source transistors coupled through corresponding control transistors that are switched using a barrel shifter to reduce variations in the bias current due to process variation. The current mirror control may be provided via a chopper amplifier to reduce flicker noise and the current mirror control voltage may be held using a track/hold circuit during transitions of the chopper amplifier to further reduce noise due to the chopping action.

    摘要翻译: 温度和过程稳定的磁场传感器偏置电流源在霍尔效应传感器电路中提供了更好的性能。 开关电容感测元件用于直接感测参考电流或偏置电流。 可以使用电流镜来产生来自参考电流的偏置电流,并且可以包括通过相应的控制晶体管耦合的多个电流源晶体管,所述控制晶体管使用桶形移位器进行切换,以减少由于过程变化引起的偏置电流的变化。 可以经由斩波放大器提供电流镜控制以减少闪烁噪声,并且可以在斩波放大器的转变期间使用轨道/保持电路来保持电流镜控制电压,以进一步减少由于斩波动作引起的噪声。

    Systems and methods for clock mode determination utilizing master clock frequency measurements
    7.
    发明授权
    Systems and methods for clock mode determination utilizing master clock frequency measurements 有权
    使用主时钟频率测量的时钟模式确定的系统和方法

    公开(公告)号:US07456765B1

    公开(公告)日:2008-11-25

    申请号:US11136030

    申请日:2005-05-24

    IPC分类号: H03M1/00

    CPC分类号: H03M1/1265 H04J3/0685

    摘要: A system for determining a data converter clock operating mode includes measurement circuitry which measures a master clock frequency of a master clock signal and a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency, the frequency ratio, and a characteristic of an additional data clock signal to an operating mode of the data converter. In another embodiment, the mapping system maps measurements of the master clock frequency alone to a data converter operating mode. In a further embodiment, the measurement circuitry measures the master clock frequency of a master clock signal, which is received directly from a master clock signal source without a modification in the master clock frequency.

    摘要翻译: 用于确定数据转换器时钟操作模式的系统包括测量主时钟信号的主时钟频率和数据时钟信号的频率与主时钟频率之间的频率比的测量电路。 映射系统将主时钟频率,频率比和附加数据时钟信号的特性的测量结果映射到数据转换器的操作模式。 在另一个实施例中,映射系统将主时钟频率的测量单独地映射到数据转换器操作模式。 在另一个实施例中,测量电路测量主时钟信号的主时钟频率,主时钟信号直接从主时钟信号源接收而不改变主时钟频率。

    Delta-sigma analog-to-digital converter (ADC) having an intermittent power-down state between conversion cycles
    8.
    发明授权
    Delta-sigma analog-to-digital converter (ADC) having an intermittent power-down state between conversion cycles 有权
    在转换周期之间具有间歇掉电状态的Delta-sigma模数转换器(ADC)

    公开(公告)号:US07365667B1

    公开(公告)日:2008-04-29

    申请号:US11534191

    申请日:2006-09-21

    IPC分类号: H03M3/00

    摘要: A delta-sigma analog to digital converter (ADC) having an intermittent power down state between conversion cycles provides for power consumption savings when the converter is in a lower sample rate operating mode. Clocks provided to the digital portions of the converter are disabled, except for a periodic interval in which a conversion is performed at the higher selectable sample rate of the converter. The analog portions of the converter can also be disabled, but are re-enabled for a predetermined time period and reset before the digital clocks are enabled, so that the loop filter and feedback value supplied from the quantizer to the loop filter are stable prior to each conversion.

    摘要翻译: 在转换周期间具有间歇掉电状态的Δ-Σ模数转换器(ADC)提供了当转换器处于较低采样率操作模式时的功耗节省。 提供给转换器的数字部分的时钟被禁用,除了在转换器的较高可选采样率下进行转换的周期性间隔之外。 转换器的模拟部分也可以被禁用,但在预定的时间周期内重新使能并在数字时钟被使能之前复位,使得从量化器提供给环路滤波器的环路滤波器和反馈值在 每次转换。

    Systems and methods for clock mode determination utilizing prioritization criteria
    9.
    发明授权
    Systems and methods for clock mode determination utilizing prioritization criteria 有权
    使用优先级标准的时钟模式确定的系统和方法

    公开(公告)号:US07352303B1

    公开(公告)日:2008-04-01

    申请号:US11135995

    申请日:2005-05-24

    IPC分类号: H03M7/00

    CPC分类号: H03M1/1255 G11B20/14

    摘要: A system for determining a data converter operating mode includes measurement circuitry that measures a master clock frequency of a master clock signal received without a modification in frequency from a master clock signal source and that measures a frequency ratio between a frequency of a data clock signal and the master clock frequency. A mapping system maps the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter. In other embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter based on mode priority constraints. In additional embodiments, mapping systems map the measurements of the master clock frequency and the frequency ratio to an operating mode of the data converter by narrowing the choices of master clock divide ratios and subsequently determining an operating mode from the frequency ratio.

    摘要翻译: 一种用于确定数据转换器操作模式的系统包括测量电路,其测量主时钟信号的主时钟频率,而无需主时钟信号源的频率修改,并且测量数据时钟信号的频率与数据时钟信号的频率之间的频率比 主时钟频率。 映射系统将主时钟频率和频率比的测量结果映射到数据转换器的操作模式。 在其他实施例中,映射系统基于模式优先级约束将主时钟频率和频率比的测量映射到数据转换器的操作模式。 在另外的实施例中,映射系统通过缩小主时钟分频比的选择并随后从频率比确定操作模式,将主时钟频率和频率比的测量值映射到数据转换器的工作模式。

    Circuits and methods for reducing the effects of level shifter delays in systems operating in multiple voltage domains
    10.
    发明授权
    Circuits and methods for reducing the effects of level shifter delays in systems operating in multiple voltage domains 有权
    用于减少在多个电压域中工作的系统中电平移位器延迟的影响的电路和方法

    公开(公告)号:US07348813B1

    公开(公告)日:2008-03-25

    申请号:US11292523

    申请日:2005-12-02

    IPC分类号: H03L7/00

    CPC分类号: H03K19/0175 H03K19/01

    摘要: A method of interfacing circuits operating in different voltage domains includes receiving a first signal with a first circuit operating in a first voltage domain and generating a second signal with a second circuit operating in a second voltage domain. The second signal is level shifted between the first and second voltage domains with a level shifter and synchronized with the first signal with a third circuit operating in the first voltage domain.

    摘要翻译: 在不同电压域中操作的电路接口的方法包括:接收具有在第一电压域中工作的第一电路的第一信号,并产生具有在第二电压域中工作的第二电路的第二信号。 第二信号在电平移位器之间在第一和第二电压域之间电平移位,并且与第一信号同步,第三电路在第一电压域中工作。