公开(公告)号：US20130120058A1

公开(公告)日：2013-05-16

申请号：US13693590

申请日：2012-12-04

Applicant: Eric Nestler ,  Gustavo Castro

Inventor： Eric Nestler ,  Gustavo Castro

IPC: H03K5/00

CPC classification number: H03K5/00 ,  H03H15/02

Abstract: A filter provides high-pass coupling between circuits. The filter includes charge storage elements and switch elements coupling the charge storage elements. A controller is coupled to the switch elements for sequencing configurations of the switch elements in phases for each of a succession of sample periods to perform a time sampled continuous value signal processing of the input signal to form the processed signal. The sequenced configurations include a configuration in which a charge representing a value of the input signal is stored on a multiple of the charge storage elements, a configuration in which charge storage elements are coupled with the switch elements, and a set of one or more configurations that implement a scaling of a charge on one of the charge storage elements to be on one or more of the charge storage elements.

Abstract translation: 滤波器提供电路之间的高通耦合。 滤波器包括电荷存储元件和耦合电荷存储元件的开关元件。 控制器耦合到开关元件，用于对开关元件的配置进行排序，以对于连续的采样周期中的每一个进行相位，以执行输入信号的时间采样连续值信号处理以形成处理的信号。 顺序配置包括其中表示输入信号的值的电荷存储在电荷存储元件的倍数上的配置，其中电荷存储元件与开关元件耦合的配置，以及一组一个或多个配置 其中一个电荷存储元件上的电荷在一个或多个电荷存储元件上实现。

公开(公告)号：US20120306569A1

公开(公告)日：2012-12-06

申请号：US13490110

申请日：2012-06-06

Applicant: Eric Nestler ,  Jeffrey Venuti ,  Vladimir Zlatkovic ,  Kartik Nanda

Inventor： Eric Nestler ,  Jeffrey Venuti ,  Vladimir Zlatkovic ,  Kartik Nanda

IPC: H03K5/00

CPC classification number: H03K5/00 ,  H03H15/02

Abstract: An approach to time domain filtering uses a passive charge sharing approach to implement an infinite impulse response filter. Delayed samples of an input signal are stored as charges on capacitors of a first array of capacitors, and delayed samples of the output signal are stored as charges on capacitors of a second array of capacitors. Outputs are determined by passively coupling capacitors of the first and second arrays to one another, and determining the output according to a total charge on the coupled capacitors. In some examples, a gain is applied to the total charge prior to storing the output on the second array of capacitors. In some examples, a charge scaling circuit is applied to the charges stored on the arrays prior to coupling capacitors to form the output.

Abstract translation: 时域滤波方法采用无源电荷共享方式来实现无限脉冲响应滤波器。 将输入信号的延迟样本作为电荷存储在第一电容器阵列的电容器上，并且输出信号的延迟采样作为电荷存储在第二电容器阵列的电容器上。 输出由第一和第二阵列的电容器彼此无源耦合确定，并根据耦合的电容器上的总电荷来确定输出。 在一些示例中，在将输出存储在第二电容器阵列之前，将增益应用于总电荷。 在一些示例中，在耦合电容器之前，将电荷量化电路应用于存储在阵列上的电荷以形成输出。

公开(公告)号：US20100220514A1

公开(公告)日：2010-09-02

申请号：US12537060

申请日：2009-08-06

Applicant: Benjamin Vigoda ,  Jeffrey Bernstein ,  Jeffrey Venuti ,  Alexander Alexeyev ,  Eric Nestler ,  David Reynolds

Inventor： Benjamin Vigoda ,  Jeffrey Bernstein ,  Jeffrey Venuti ,  Alexander Alexeyev ,  Eric Nestler ,  David Reynolds

IPC: G11C11/24 ,  G11C7/00

CPC classification number: G11C27/005 ,  G11C7/16 ,  G11C8/10 ,  G11C11/5642 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C29/00 ,  G11C2013/0092 ,  G11C2211/5634

Abstract: A storage device includes a storage array having a group of storage elements. Each storage element can written to a discrete set of physical states. A read circuit selects one or more storage elements and generates, for each selected storage element, an analog signal representative of the physical state of the selected storage element. A signal processing circuit processes the analog signal to generate a plurality of outputs, with each output representing a degree of an association of the selected storage element with a different subset of one or more of the discrete set of physical states.

公开(公告)号：US20080079708A1

公开(公告)日：2008-04-03

申请号：US11904931

申请日：2007-09-28

Applicant: Abhishek Bandyopadhyay ,  Eric Nestler ,  Michael Ashburn

Inventor： Abhishek Bandyopadhyay ,  Eric Nestler ,  Michael Ashburn

IPC: G09G5/00

CPC classification number: G09G3/3696 ,  G09G3/3233 ,  G09G3/3681 ,  G09G3/3692 ,  G09G2310/0289 ,  G09G2330/02 ,  G09G2330/04

Abstract: A low voltage driver for a higher voltage LCD includes a plurality of LCD drive bias voltage input-terminals; an LCD drive voltage output terminal; an input transistor switching circuit having at least one switch for each LCD drive bias voltage for selecting one of the bias voltages; an output transistor switching circuit, responsive to the input transistor switching circuit, for applying the selected one of the bias voltages to the LCD drive voltage output terminal, the transistors of the switching circuits having a predetermined breakdown voltage; a level shifter for providing switching voltages counterpart to the plurality of bias voltages; a logic circuit for enabling the first transistor switching circuit to select a one of the bias voltages and applying a set of counterpart switching voltages to the input and output transistor switching circuits for connecting the selected one of the bias voltages to the output terminal and applying a set of switching voltages to the input and output switching circuits which limit the voltage across the transistor junctions in the switching circuit to less than the predetermined breakdown voltage.

Abstract translation: 用于较高电压LCD的低电压驱动器包括多个LCD驱动偏置电压输入端子; LCD驱动电压输出端子; 输入晶体管切换电路，具有用于每个LCD驱动偏置电压的至少一个开关，用于选择所述偏置电压之一; 输出晶体管切换电路，响应于输入晶体管切换电路，将所选择的一个偏置电压施加到LCD驱动电压输出端，开关电路的晶体管具有预定的击穿电压; 电平移位器，用于提供与多个偏置电压相对应的开关电压; 逻辑电路，用于使第一晶体管开关电路能够选择一个偏置电压，并将一组对应的开关电压施加到输入和输出晶体管开关电路，用于将所选择的一个偏置电压连接到输出端子，并施加一个 一组开关电压到输入和输出开关电路，其将开关电路中的晶体管结两端的电压限制到小于预定的击穿电压。

公开(公告)号：US06879274B2

公开(公告)日：2005-04-12

申请号：US10785831

申请日：2004-02-24

Applicant: Eric Nestler ,  Paul Daigle ,  Michael A. Ashburn, Jr.

Inventor： Eric Nestler ,  Paul Daigle ,  Michael A. Ashburn, Jr.

IPC: H03M1/06 ,  H03M1/12

CPC classification number: H03M1/124

Abstract: An analog-to-digital metering circuit includes a first programmable gain amplifier to amplify a first voltage signal from a first channel before being received by a first analog-to-digital converter that converts the amplified first voltage signal to a first digital signal. A second programmable gain amplifier amplifies a second voltage signal from a second channel and feds the amplified signal to a second analog-to-digital converter that converts the amplified second voltage signal to a second digital signal. A first lowpass filter circuit receives the first and second digital signals, to generate therefrom, a multi-bit analog-to-digital value. A direct digital synthesizer generates a digital signal representing a predetermined waveform that is fed to a digital-to-analog converter. The second voltage signal and the digital signal representing the predetermined waveform are multiplied together to generate a digital value. Phase shifting circuitry provides a signal representing a 90-degree phase shift of the digital value and a signal representing a 0-degree phase shift of the digital value. RMS circuitry converts the 0-degree phase digital signal into an In-Phase signal and the 90-degree phase digital signal into a Quadrature signal.

Abstract translation: 模拟数字计量电路包括第一可编程增益放大器，用于在被放大的第一电压信号转换为第一数字信号的第一模数转换器接收之前放大来自第一通道的第一电压信号。 第二可编程增益放大器放大来自第二通道的第二电压信号，并将放大的信号调制到第二模数转换器，其将放大的第二电压信号转换为第二数字信号。 第一低通滤波器电路接收第一和第二数字信号，从而产生多位模数值。 直接数字合成器产生表示被馈送到数模转换器的预定波形的数字信号。 将表示预定波形的第二电压信号和数字信号相乘以产生数字值。 相移电路提供表示数字值的90度相移的信号和表示数字值的0度相移的信号。 RMS电路将0度相位数字信号转换为同相信号，将90度相位数字信号转换为正交信号。

公开(公告)号：US06781361B2

公开(公告)日：2004-08-24

申请号：US10132912

申请日：2002-04-26

Applicant: Eric Nestler

Inventor： Eric Nestler

IPC: G01R700

CPC classification number: G01R21/133 ,  G01R21/127

Abstract: A power metering system including a first modulator receiving a first analog voltage associated with a current and outputting a first digitized signal. A second modulator receives a second analog voltage and outputs a second digitized signal. A first lowpass filter filters out high frequency noise associated with the first signal and decimates the frequency of the first digitized signal. The first lowpass filter outputs a first filtered signal. An interpolator performs up sampling of the signal associated with the first filtered signal. The interpolator outputs a first up sampled signal. An integrator integrates the first up sampled signal. The integrator outputs an integrated signal. A first multiplier multiplies the second digitized signal and integrated signal, and outputs a multiplied signal. The multiplied signal being used to measure power.

Abstract translation: 一种电力计量系统，包括接收与电流相关联的第一模拟电压并输出第一数字化信号的第一调制器。 第二调制器接收第二模拟电压并输出第二数字化信号。 第一低通滤波器滤除与第一信号相关联的高频噪声并抽取第一数字化信号的频率。 第一个低通滤波器输出第一个滤波信号。 内插器执行与第一滤波信号相关联的信号的采样。 内插器输出第一上采样信号。 积分器集成了第一个上采样信号。 积分器输出积分信号。 第一乘法器将第二数字化信号和积分信号相乘，并输出相乘的信号。 倍增信号用于测量功率。

公开(公告)号：US5872469A

公开(公告)日：1999-02-16

申请号：US626136

申请日：1996-04-05

Applicant: Eric Nestler

Inventor： Eric Nestler

IPC: G11C27/02

CPC classification number: G11C27/026

Abstract: A sampling capacitor interface circuit for storing charge on a sampling capacitor related to a sample of an input signal voltage during a charging phase and to transfer the stored charge to an output during a charge transfer phase, such input signal having bipolar voltages within a range above and below an input signal common mode voltage. The interface circuit includes a transistor having: an input electrode fed by the input signal; an output electrode coupled to the sampling capacitor; and, a control electrode. A controller is provided for producing a control signal having a first voltage during the charging phase and a second voltage during the charge transfer phase, such voltages being a unipolar voltage referenced to the input signal common mode voltage. A bias circuit is coupled to the input signal and has a level shifting capacitor coupled between the controller and the control electrode for storing a voltage during the charge transfer phase and for shifting the first voltage by the stored voltage during the charging phase to provide a voltage at the control electrode with a level sufficiently below the input signal common mode voltage to bias the transistor to a conducting condition during the charging phase over the range of input signal voltages.

Abstract translation: 一种采样电容器接口电路，用于在充电阶段期间在与输入信号电压的采样相关的采样电容器上存储电荷，并且在电荷转移阶段将所存储的电荷传送到输出端，这样的输入信号具有在上述范围内的双极性电压 并低于输入信号共模电压。 接口电路包括晶体管，具有：通过输入信号馈送的输入电极; 耦合到采样电容器的输出电极; 和控制电极。 提供控制器，用于在充电阶段产生具有第一电压的控制信号和电荷转移阶段期间的第二电压，这样的电压是参考输入信号共模电压的单极电压。 偏置电路耦合到输入信号，并且具有耦合在控制器和控制电极之间的电平移动电容器，用于在电荷转移阶段期间存储电压，并且在充电阶段期间通过存储的电压移动第一电压以提供电压 在控制电极处具有足够低于输入信号共模电压的电平，以在输入信号电压范围内的充电阶段将晶体管偏置到导通状态。

公开(公告)号：US09479866B2

公开(公告)日：2016-10-25

申请号：US13428496

申请日：2012-03-23

Applicant: Robert Adams ,  David Hossack ,  Benjamin Vigoda ,  Eric Nestler ,  Mira Wilczek

Inventor： Robert Adams ,  David Hossack ,  Benjamin Vigoda ,  Eric Nestler ,  Mira Wilczek

IPC: H04R3/00

CPC classification number: H04R3/005 ,  H04R2499/13

Abstract: Microphone stages in a microphone array may be coupled together in a daisy chain. Each stage may include a microphone, an analog to digital converter, a decimation unit, a receiver, an adder, and a transmitter. The converter may convert analog audio microphone signals into digital codes that may be decimated. The adder may add decimated digital codes in each stage to a cumulative sum of decimated digital codes from prior stages. This new sum may be transmitted to the next microphone stage, where the adder may add the decimated digital codes from that stage to the cumulative sum. A serial interface may be used to connect the transmitters and receivers of each of the stages. The serial interface may be used to transmit the cumulative sum of decimated digital codes between the stages. The serial interface may also be used to transmit configuration data between the stages.

Abstract translation: 麦克风阵列中的麦克风级可以以菊花链耦合在一起。 每个阶段可以包括麦克风，模数转换器，抽取单元，接收器，加法器和发射器。 转换器可将模拟音频麦克风信号转换为可能被抽取的数字代码。 加法器可以将每个级中的抽取的数字代码添加到来自前一级的抽取的数字代码的累积和。 这个新的和可以传送到下一个麦克风阶段，其中加法器可以将从该阶段抽取的数字代码添加到累积和。 可以使用串行接口连接每个级的发射机和接收机。 串行接口可以用于在级之间传送抽取的数字代码的累加和。 串行接口也可用于在各个级之间传输配置数据。

公开(公告)号：US08188753B2

公开(公告)日：2012-05-29

申请号：US12545590

申请日：2009-08-21

Applicant: Eric Nestler ,  Vladimir Zlatkovic

Inventor： Eric Nestler ,  Vladimir Zlatkovic

IPC: G01R27/26

CPC classification number: H03H15/02 ,  G01D5/24 ,  G01R27/2605 ,  G01R31/028 ,  G06F17/14 ,  G06G7/19

Abstract: Some general aspects of the invention relate to a circuit and to a method for analog computation, for example, using switched capacitor integrated circuits. In some examples, a circuit includes a first group of capacitors and a second group of capacitors that may store charges during circuit operation. The first and/or the second group of capacitors may include multiple disjoint subsets of capacitors. An input circuit is provided for receiving a set of input signals and for inducing a charge on each of some or all capacitors in the first group of capacitors according to a corresponding input signal. Switches, for example, transistors controlled by a sequence of clock signals, are used to couple different sets of capacitors. Different configurations of the switches are used to form different sets of the capacitors among which charge can redistribute.

Abstract translation: 本发明的一些一般方面涉及电路和模拟计算的方法，例如使用开关电容器集成电路。 在一些示例中，电路包括第一组电容器和可在电路操作期间存储电荷的第二组电容器。 第一和/或第二组电容器可以包括电容器的多个不相交的子集。 提供输入电路，用于根据相应的输入信号接收一组输入信号并用于在第一组电容器中的一些或全部电容器的每一个上感应电荷。 开关，例如，由一系列时钟信号控制的晶体管，用于耦合不同组的电容器。 开关的不同配置用于形成不同的电容器组，其中电荷可重新分布。

公开(公告)号：US06916603B2

公开(公告)日：2005-07-12

申请号：US09939709

申请日：2001-08-28

Applicant: Roland E. Baron ,  Natalie Sims ,  Georgios Sabatakos ,  Eric Nestler ,  Jingshan Chen ,  Max Kelz

Inventor： Roland E. Baron ,  Natalie Sims ,  Georgios Sabatakos ,  Eric Nestler ,  Jingshan Chen ,  Max Kelz

IPC: G01N33/48 ,  A01K67/027 ,  A61K31/00 ,  A61K45/00 ,  A61K48/00 ,  A61P19/08 ,  A61P19/10 ,  A61P43/00 ,  C07H21/04 ,  C12N5/06 ,  C12N15/09 ,  C12N15/63 ,  C12N15/74 ,  C12Q1/00 ,  C12Q1/02 ,  C12Q1/68 ,  G01N1/30 ,  G01N33/00 ,  G01N33/15 ,  G01N33/50 ,  G01N33/53 ,  G01N33/566 ,  G01N33/68

CPC classification number: A01K67/0275 ,  A01K2217/05 ,  A01K2227/105 ,  A01K2267/035 ,  A61K31/00 ,  A61K48/00 ,  G01N33/6893

Abstract: The present invention is based on the discovery that overexpression of ΔFosB leads to bone formation and that ΔFosB expression inhibits adipogenesis. The present invention provides methods of identifying agents that modulate bone formation and adipogenesis. Moreover, the present invention provides methods for identifying genes that are modulated by ΔFosB and that modulates ΔFosB, osteogenesis, and adipogenesis.

Abstract translation: 本发明基于以下发现：DeltaFosB的过度表达导致骨形成并且DeltaFosB表达抑制脂肪形成。 本发明提供鉴定调节骨形成和脂肪形成的药剂的方法。 此外，本发明提供了鉴定由DeltaFosB调节并调节DeltaFosB，成骨和脂肪形成的基因的方法。