公开(公告)号：US20100213545A1

公开(公告)日：2010-08-26

申请号：US12601821

申请日：2008-05-15

申请人： Ching Tee Elizabeth Kho ,  Mee Guoh Michael Tiong ,  Kia Yaw Kee ,  Wen Jun Li ,  Wenyi Li ,  Michael May ,  Chean Chian Alain Liew

发明人： Ching Tee Elizabeth Kho ,  Mee Guoh Michael Tiong ,  Kia Yaw Kee ,  Wen Jun Li ,  Wenyi Li ,  Michael May ,  Chean Chian Alain Liew

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/1041 ,  H01L29/0653 ,  H01L29/0692 ,  H01L29/1083 ,  H01L29/42368 ,  H01L29/4916 ,  H01L29/66659 ,  H01L29/7833 ,  H01L29/7835

摘要： The present invention provides a method for fabricating a MOS transistor (100) with suppression of edge transistor effect. In one embodiment of an NMOS, an elongate implant limb (110, HOa, 114) extends from each of two sidewalls (14a, 14b) of a p-type well (14) to partially wrap around each respective longitudinal end of the gate (20) and to overlay a portion thereof. In another embodiment, the elongate implant limb (110, 110a) extends into the drain/source drift region (32, 42). The NMOS transistor (100) thus fabricated allows the NMOS transistor to operate at relatively high voltages with reduced drain leakage current but with no additional masks or process time in the process integration.

摘要翻译： 本发明提供一种抑制边缘晶体管效应的制造MOS晶体管（100）的方法。 在NMOS的一个实施例中，细长植入肢（110，110a，114）从p型阱（14）的两个侧壁（14a，14b）中的每一个延伸，以部分地围绕浇口的各个纵向端 20）并覆盖其一部分。 在另一个实施例中，细长植入肢（110,110a）延伸进入漏/源漂移区（32,42）。 如此制造的NMOS晶体管（100）允许NMOS晶体管在相对较高的电压下工作，具有降低的漏极泄漏电流，但是在处理集成中没有额外的掩模或处理时间。

公开(公告)号：US20140342518A1

公开(公告)日：2014-11-20

申请号：US14274773

申请日：2014-05-12

申请人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

发明人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

IPC分类号： H01L29/66 ,  H01L21/28 ,  H01L29/08 ,  H01L29/423

CPC分类号： H01L29/66734 ,  H01L21/28114 ,  H01L21/28238 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813

摘要： A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

摘要翻译： 功率MOSFET包括具有上表面的半导体衬底，衬底中的第一深度的腔，其侧壁延伸到上表面，空腔中的电介质衬垫，介电衬里内的延伸到上表面或上表面的栅极导体 在第二深度的衬底内的体区域，其在第一厚度的电介质衬垫的第一部分和主体区域中的源区域之间与下腔体区域中的栅极导体分开（ s）延伸到小于第二深度的第三深度。 源极区域通过第二厚度的电介质衬垫的第二部分至少部分地大于第一厚度与栅极导体分离。 电介质衬垫具有在或小于第三深度的横向延伸到门导体远离身体区域的突起。

公开(公告)号：US20130299898A1

公开(公告)日：2013-11-14

申请号：US13609281

申请日：2012-09-11

申请人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

发明人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/66734 ,  H01L21/28114 ,  H01L21/28238 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813

摘要： A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

摘要翻译： 功率MOSFET包括具有上表面的半导体衬底，衬底中的第一深度的腔，其侧壁延伸到上表面，空腔中的电介质衬垫，介电衬垫内的延伸到上表面或上表面的栅极导体 在第二深度的衬底内的体区域，其在第一厚度的电介质衬垫的第一部分和主体区域中的源区域之间与下腔体区域中的栅极导体分开（ s）延伸到小于第二深度的第三深度。 源极区域通过第二厚度的电介质衬垫的第二部分至少部分地大于第一厚度与栅极导体分离。 电介质衬垫具有在或小于第三深度的横向延伸到门导体远离身体区域的突起。

公开(公告)号：US07532324B2

公开(公告)日：2009-05-12

申请号：US11877316

申请日：2007-10-23

申请人： Muqing Liu ,  Xiaoli Zhou ,  Wenyi Li ,  Wanlu Zhang ,  Chuan Yuan

发明人： Muqing Liu ,  Xiaoli Zhou ,  Wenyi Li ,  Wanlu Zhang ,  Chuan Yuan

IPC分类号： G01J3/28

CPC分类号： G01J3/46 ,  G01J3/0251 ,  G01J3/465 ,  G01J2001/4252

摘要： This invention belongs to the luminous flux measurement field, and especially relates to the equipment and method for LED's total luminous flux measurement with a narrow beam standard light source. The system for LED's total luminous flux measurement with a narrow beam standard light source in this invention comprises an integrating sphere, the light source, a narrow aperture fiber, a spectrometer and a driver for the light source. The light source is lighted by the driver. The narrow beam standard light source (both luminous flux standard and spectrum standard) is placed on the interior surface of integrating sphere, there is not any baffle in the sphere, and a narrow aperture fiber transfers the light to a multi-channel spectrometer which measures the spectrum distribution of LED and calculates its total luminous flux. The equipment in this invention is easy to use, has small error and low cost, and can achieve accurate results for LED's total luminous flux.

摘要翻译： 本发明属于光通量测量领域，特别涉及用窄光标准光源进行LED全光束测量的设备和方法。 本发明的用于具有窄光束标准光源的LED的总光通量测量系统包括积分球，光源，窄孔光纤，光谱仪和用于光源的驱动器。 光源由驾驶员点亮。 窄光束标准光源（光通量标准和光谱标准）放置在积分球的内表面上，球体中没有任何挡板，窄光纤光纤将光传输到多通道光谱仪，该光谱仪测量 LED的光谱分布并计算其总光通量。 本发明的设备易于使用，误差小，成本低，可以实现LED全光通量的准确结果。

公开(公告)号：US08932928B2

公开(公告)日：2015-01-13

申请号：US14274773

申请日：2014-05-12

申请人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

发明人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

IPC分类号： H01L21/336 ,  H01L29/78 ,  H01L29/66 ,  H01L29/423 ,  H01L21/28 ,  H01L29/08

CPC分类号： H01L29/66734 ,  H01L21/28114 ,  H01L21/28238 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813

摘要： A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

摘要翻译： 功率MOSFET包括具有上表面的半导体衬底，衬底中的第一深度的腔，其侧壁延伸到上表面，空腔中的电介质衬垫，介电衬里内的延伸到上表面或上表面的栅极导体 在第二深度的衬底内的体区域，其在第一厚度的电介质衬垫的第一部分和主体区域中的源区域之间与下腔体区域中的栅极导体分开（ s）延伸到小于第二深度的第三深度。 源极区域通过第二厚度的电介质衬垫的第二部分至少部分地大于第一厚度与栅极导体分离。 电介质衬垫具有在或小于第三深度的横向延伸到门导体远离身体区域的突起。

公开(公告)号：US20080129996A1

公开(公告)日：2008-06-05

申请号：US11877316

申请日：2007-10-23

申请人： Muqing Liu ,  Xiaoli Zhou ,  Wenyi Li ,  Wanlu Zhang ,  Chuan Yuan

发明人： Muqing Liu ,  Xiaoli Zhou ,  Wenyi Li ,  Wanlu Zhang ,  Chuan Yuan

IPC分类号： G01J3/28

CPC分类号： G01J3/46 ,  G01J3/0251 ,  G01J3/465 ,  G01J2001/4252

摘要： This invention belongs to the luminous flux measurement field, and especially relates to the equipment and method for LED's total luminous flux measurement with a narrow beam standard light source. The system for LED's total luminous flux measurement with a narrow beam standard light source in this invention comprises an integrating sphere, the light source, a narrow aperture fiber, a spectrometer and a driver for the light source. The light source is lighted by the driver. The narrow beam standard light source (both luminous flux standard and spectrum standard) is placed on the interior surface of integrating sphere, there is not any baffle in the sphere, and a narrow aperture fiber transfers the light to a multi-channel spectrometer which measures the spectrum distribution of LED and calculates its total luminous flux. The equipment in this invention is easy to use, has small error and low cost, and can achieve accurate results for LED's total luminous flux.

摘要翻译： 本发明属于光通量测量领域，特别涉及用窄光标准光源进行LED全光束测量的设备和方法。 本发明的用于具有窄光束标准光源的LED的总光通量测量系统包括积分球，光源，窄孔光纤，光谱仪和用于光源的驱动器。 光源由驾驶员点亮。 窄光束标准光源（光通量标准和光谱标准）放置在积分球的内表面上，球体中没有任何挡板，窄光纤光纤将光传输到多通道光谱仪，该光谱仪测量 LED的光谱分布并计算其总光通量。 本发明的设备易于使用，误差小，成本低，可以实现LED全光通量的准确结果。

公开(公告)号：US08759909B2

公开(公告)日：2014-06-24

申请号：US13609281

申请日：2012-09-11

申请人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

发明人： Peilin Wang ,  Edouard D. de Fresart ,  Wenyi Li

IPC分类号： H01L21/336

CPC分类号： H01L29/66734 ,  H01L21/28114 ,  H01L21/28238 ,  H01L29/086 ,  H01L29/0865 ,  H01L29/0869 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/42376 ,  H01L29/7813

摘要： A power MOSFET includes a semiconductor substrate with an upper surface, a cavity of a first depth in the substrate whose sidewall extends to the upper surface, a dielectric liner in the cavity, a gate conductor within the dielectric liner extending to or above the upper surface, body region(s) within the substrate of a second depth, separated from the gate conductor in a lower cavity region by first portion(s) of the dielectric liner of a first thickness, and source region(s) within the body region(s) extending to a third depth that is less than the second depth. The source region(s) are separated from the gate conductor by a second portion of the dielectric liner of a second thickness at least in part greater than the first thickness. The dielectric liner has a protrusion extending laterally into the gate conductor away from the body region(s) at or less than the third depth.

摘要翻译： 功率MOSFET包括具有上表面的半导体衬底，衬底中的第一深度的腔，其侧壁延伸到上表面，空腔中的电介质衬垫，介电衬里内的延伸到上表面或上表面的栅极导体 在第二深度的衬底内的体区域，其在第一厚度的电介质衬垫的第一部分和主体区域中的源区域之间与下腔体区域中的栅极导体分开（ s）延伸到小于第二深度的第三深度。 源极区域通过第二厚度的电介质衬垫的第二部分至少部分地大于第一厚度与栅极导体分离。 电介质衬垫具有在或小于第三深度的横向延伸到门导体远离身体区域的突起。

公开(公告)号：US09293535B2

公开(公告)日：2016-03-22

申请号：US13610901

申请日：2012-09-12

申请人： Peilin Wang ,  Jingjing Chen ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Wenyi Li ,  Ganming Qin

发明人： Peilin Wang ,  Jingjing Chen ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Wenyi Li ,  Ganming Qin

IPC分类号： H01L29/66 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08

CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7815

摘要： A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET (304) to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.

摘要翻译： 功率MOSFET具有主FET（MFET）和嵌入式电流感测FET（SFET）。 MFET栅极流道通过MFET和SFET之间的缓冲空间中的隔离栅极流道（IGR）耦合到SFET栅极流道。 在一个实施例中，n IGR（i = 1至n）将MFET（304）的第一部分的n + 1个栅极耦合到SFET的n个栅极。 IGR具有曲折的中心部分，其中每个SFET栅极流道经由IGR耦合到两个MFET栅极流道。 曲折的中心部分提供阻挡除了第一和最后一次IGR的外侧之外的所有IGR的SFET源和MFET源之间的寄生泄漏路径。 这些可能通过在围绕剩余泄漏路径的区域中增加体掺杂来阻止。 IGR基本上没有源区。

公开(公告)号：US20140159146A1

公开(公告)日：2014-06-12

申请号：US14072763

申请日：2013-11-05

申请人： Peilin Wang ,  EDOUARD DE FRESART ,  WENYI LI

发明人： Peilin Wang ,  EDOUARD DE FRESART ,  WENYI LI

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/66734 ,  H01L29/0869 ,  H01L29/1095 ,  H01L29/41766 ,  H01L29/66727 ,  H01L29/7813

摘要： A trench gate transistor is formed from a semiconductor substrate with its upper surface covered in an oxide dielectric layer. The trench gate transistor has a drain region, a body region, source region and a trench lined with a gate insulator that electrically insulates a conductive gate electrode formed in the trench from the body region. The body region has a sloping upper surface that extends away from the trench towards the drain region. The sloping upper surface is formed by exposing the oxide dielectric layer to an oxidized atmosphere, through an opening in a mask, so as to form a dielectric region. The dielectric region includes the oxide dielectric layer and a sacrificial area of the semiconductor substrate.

摘要翻译： 沟槽栅极晶体管由其上表面覆盖在氧化物介电层中的半导体衬底形成。 沟槽栅极晶体管具有漏极区域，体区域，源极区域和衬有栅极绝缘体的沟槽，该栅极绝缘体将形成在沟槽中的导电栅电极与身体区域电绝缘。 身体区域具有倾斜的上表面，其从沟槽朝向漏区延伸。 倾斜的上表面通过将氧化物介电层通过掩模中的开口暴露于氧化气氛而形成电介质区域。 电介质区域包括氧化物电介质层和半导体衬底的牺牲区域。

公开(公告)号：US20140070313A1

公开(公告)日：2014-03-13

申请号：US13610901

申请日：2012-09-12

申请人： Peilin Wang ,  Jingjing Chen ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Wenyi Li ,  Ganming Qin

发明人： Peilin Wang ,  Jingjing Chen ,  Edouard D. de Fresart ,  Pon Sung Ku ,  Wenyi Li ,  Ganming Qin

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/1095 ,  H01L29/0696 ,  H01L29/0865 ,  H01L29/4238 ,  H01L29/66734 ,  H01L29/7815

摘要： A power MOSFET has a main-FET (MFET) and an embedded current sensing-FET (SFET). MFET gate runners are coupled to SFET gate runners by isolation gate runners (IGRs) in a buffer space between the MFET and the SFET. In one embodiment, n IGRs (i=1 to n) couple n+1 gates of a first portion of the MFET (304) to n gates of the SFET. The IGRs have zigzagged central portions where each SFET gate runner is coupled via the IGRs to two MFET gate runners. The zigzagged central portions provide barriers that block parasitic leakage paths, between sources of the SFET and sources of the MFET, for all IGRs except the outboard sides of the first and last IGRs. These may be blocked by increasing the body doping in regions surrounding the remaining leakage paths. The IGRs have substantially no source regions.

摘要翻译： 功率MOSFET具有主FET（MFET）和嵌入式电流感测FET（SFET）。 MFET栅极流道通过MFET和SFET之间的缓冲空间中的隔离栅极流道（IGR）耦合到SFET栅极流道。 在一个实施例中，n IGR（i = 1至n）将MFET（304）的第一部分的n + 1个栅极耦合到SFET的n个栅极。 IGR具有曲折的中心部分，其中每个SFET栅极流道经由IGR耦合到两个MFET栅极流道。 曲折的中心部分提供阻挡除了第一和最后一次IGR的外侧之外的所有IGR的SFET源和MFET源之间的寄生泄漏路径。 这些可能通过在围绕剩余泄漏路径的区域中增加体掺杂来阻止。 IGRs基本上没有源区。