公开(公告)号：US07210081B1

公开(公告)日：2007-04-24

申请号：US10465139

申请日：2003-06-19

申请人： Bruce Euzent ,  Roy Wei-Guang Wu ,  Jeffrey Barton ,  Anil Pannikkat ,  Vadali Mahadev ,  Tomas Jonsson

发明人： Bruce Euzent ,  Roy Wei-Guang Wu ,  Jeffrey Barton ,  Anil Pannikkat ,  Vadali Mahadev ,  Tomas Jonsson

IPC分类号： G01R31/28

CPC分类号： G01R31/2803 ,  G01R31/2818 ,  G01R31/318516

摘要： An apparatus performs reliability assessment of electronic hardware. The apparatus includes a test assembly. The test assembly includes at least one programmable logic device (PLD). The PLD is configured to provide a logic function, such as the function of a plurality of inverters coupled in a cascade manner. The apparatus further includes a signal source coupled to the test assembly. The signal source provides a stimulus signal to the test assembly. The apparatus also includes a signal monitor coupled to the test assembly. The signal monitor monitors a response signal generated by the test assembly.

摘要翻译： 一种装置执行电子硬件的可靠性评估。 该装置包括一个测试组件。 测试组件包括至少一个可编程逻辑器件（PLD）。 PLD被配置为提供诸如以级联方式耦合的多个反相器的功能的逻辑功能。 该装置还包括耦合到测试组件的信号源。 信号源向测试组件提供刺激信号。 该装置还包括耦合到测试组件的信号监视器。 信号监视器监视由测试组件产生的响应信号。

公开(公告)号：US07741160B1

公开(公告)日：2010-06-22

申请号：US12535624

申请日：2009-08-04

申请人： Wen-chou Vincent Wang ,  Yuan Li ,  Bruce Euzent ,  Vadali Mahadev

发明人： Wen-chou Vincent Wang ,  Yuan Li ,  Bruce Euzent ,  Vadali Mahadev

IPC分类号： H01L21/44

CPC分类号： H01L23/3128 ,  H01L21/50 ,  H01L21/563 ,  H01L23/16 ,  H01L24/31 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00 ,  H01L2924/3512

摘要： Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.

摘要翻译： 提供了半导体管芯倒装芯片封装和半导体管芯倒装芯片封装元件，其中封装/部件的某些特性被控制以便于封装应力的管理。 还提供了用于这种包装和包装部件的制造方法。 例如，可以控制模具的厚度，使得由模具产生/经历的应力最小化。 因此，封装应力被控制到适合于并入低K Si管芯和/或薄封装衬底的水平。 此外，在半导体管芯倒装芯片封装的制造期间，可以将薄模具附接到散热器以增加刚性以便于更容易的处理。

公开(公告)号：US08212353B1

公开(公告)日：2012-07-03

申请号：US12778905

申请日：2010-05-12

申请人： Wen-chou Vincent Wang ,  Yuan Li ,  Bruce Euzent ,  Vadali Mahadev

发明人： Wen-chou Vincent Wang ,  Yuan Li ,  Bruce Euzent ,  Vadali Mahadev

IPC分类号： H01L23/34

CPC分类号： H01L23/3128 ,  H01L21/50 ,  H01L21/563 ,  H01L23/16 ,  H01L24/31 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00 ,  H01L2924/3512

摘要： Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.

摘要翻译： 提供了半导体管芯倒装芯片封装和半导体管芯倒装芯片封装元件，其中封装/部件的某些特性被控制以便于封装应力的管理。 还提供了用于这种包装和包装部件的制造方法。 例如，可以控制模具的厚度，使得由模具产生/经历的应力最小化。 因此，封装应力被控制到适合于并入低K Si管芯和/或薄封装衬底的水平。 此外，在半导体管芯倒装芯片封装的制造期间，可以将薄模具附接到散热器以增加刚性以便于更容易的处理。

公开(公告)号：US07585702B1

公开(公告)日：2009-09-08

申请号：US11270676

申请日：2005-11-08

申请人： Wen-chou Vincent Wang ,  Yuan Li ,  Bruce Euzent ,  Vadali Mahadev

发明人： Wen-chou Vincent Wang ,  Yuan Li ,  Bruce Euzent ,  Vadali Mahadev

IPC分类号： H01L21/44

CPC分类号： H01L23/3128 ,  H01L21/50 ,  H01L21/563 ,  H01L23/16 ,  H01L24/31 ,  H01L24/81 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2224/81801 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/00 ,  H01L2924/3512

摘要： Provided are semiconductor die flip chip packages and semiconductor die flip chip package components where certain properties of the packages/components are controlled to facilitate management of the package stresses. Also provided are fabrication methods for such packages and package components. For instance, the thickness of a die can be controlled such that the stress generated/experienced by the die is minimized. As such, the package stress is managed to suitable levels for incorporation of a low-K Si die and/or a thin package substrate. Further, a thin die can be attached to a heat spreader to increase the rigidity for easier handling during fabrication of the semiconductor die flip chip package.

摘要翻译： 提供了半导体管芯倒装芯片封装和半导体管芯倒装芯片封装元件，其中封装/部件的某些特性被控制以便于封装应力的管理。 还提供了这种包装和包装部件的制造方法。 例如，可以控制模具的厚度，使得由模具产生/经历的应力最小化。 因此，封装应力被控制到适合于并入低K Si管芯和/或薄封装衬底的水平。 此外，在半导体管芯倒装芯片封装的制造期间，可以将薄模具附接到散热器以增加刚性以便于更容易的处理。