公开(公告)号：US07633348B2

公开(公告)日：2009-12-15

申请号：US11706199

申请日：2007-02-15

申请人： Yong Jheng Lin ,  Wen Hsiang Huang ,  Min-Yi Chen

发明人： Yong Jheng Lin ,  Wen Hsiang Huang ,  Min-Yi Chen

IPC分类号： H03L7/099 ,  G06F13/00

CPC分类号： H03L7/085 ,  H03L7/0991 ,  H03L7/181 ,  H04L7/033

摘要： A frequency-locking device including a digitally-controlled oscillator (DCO) and a comparing unit is disclosed. The DCO is used for generating an output frequency signal. The comparing unit receives a Keep Alive signal from a universal serial bus (USB) and the output frequency signal, and compares the Keep Alive signal with the output frequency signal to generate a calibration signal. Then, the DCO adjusts the frequency of the output frequency signal according to the calibration signal to meet the USB specification for data communication.

摘要翻译： 公开了一种包括数字控制振荡器（DCO）和比较单元的频率锁定装置。 DCO用于产生输出频率信号。 比较单元从通用串行总线（USB）和输出频率信号接收Keep Alive信号，并将Keep Alive信号与输出频率信号进行比较，以产生校准信号。 然后，DCO根据校准信号调整输出频率信号的频率，以符合USB规范进行数据通信。

公开(公告)号：US20090187735A1

公开(公告)日：2009-07-23

申请号：US12357779

申请日：2009-01-22

申请人： Chien-Liang Lin ,  Wen-Hsiang Huang ,  Hao-Jan Chen

发明人： Chien-Liang Lin ,  Wen-Hsiang Huang ,  Hao-Jan Chen

IPC分类号： G06F15/76 ,  G06F9/02

CPC分类号： G06F15/7814

摘要： A microcontroller having dual-core architecture is provided. Using a unique hardware configuration of memories, control registers and reset machines, the invention not only reduces hardware cost, but also improves management efficiency and system stability.

摘要翻译： 提供了具有双核架构的微控制器。 使用存储器，控制寄存器和复位机的独特硬件配置，本发明不仅降低了硬件成本，而且提高了管理效率和系统稳定性。

公开(公告)号：US20080123726A1

公开(公告)日：2008-05-29

申请号：US11976285

申请日：2007-10-23

申请人： Yong Jheng Lin ,  Wen Hsiang Huang ,  Min-Yi Chen

发明人： Yong Jheng Lin ,  Wen Hsiang Huang ,  Min-Yi Chen

IPC分类号： H03L7/00

CPC分类号： H03L7/06 ,  H04L7/10

摘要： The invention proposes a simple method suitable for automatically locking frequency during USB data communication. Based on the soft plug/unplug concept proposed in the contents and the error handling mechanism defined in the USB specification, we can calibrate the clock frequency of the digitally controlled oscillator (DCO), through the token packets, to be within the acceptable frequency when USB device is attached to the host controller.

摘要翻译： 本发明提出了一种适用于在USB数据通信期间自动锁定频率的简单方法。 基于内容中提出的软插拔概念和USB规范中定义的错误处理机制，我们可以通过令牌包将数字控制振荡器（DCO）的时钟频率校准到可接受的频率范围内 USB设备连接到主机控制器。

公开(公告)号：US06594809B2

公开(公告)日：2003-07-15

申请号：US09725825

申请日：2000-11-29

申请人： Shao-Yu Wang ,  Wen-Hsiang Huang ,  Hsiao-Pin Su ,  Jun-Jyeh Hsiao

发明人： Shao-Yu Wang ,  Wen-Hsiang Huang ,  Hsiao-Pin Su ,  Jun-Jyeh Hsiao

IPC分类号： G06F1750

CPC分类号： H01L27/0629 ,  G06F17/5068

摘要： Antenna diodes used to correct antenna rule violations during the design and formation of integrated circuits are defined within filler cells laid out on the IC chip following the layout of standard electronic module cells and routing of electrical conductors on the chip. The filler cells are disposed in gaps between standard cells containing the electronic modules. The diodes are formed in unconnected pairs that are selectively connected to each other and to an adjacent conductor in order to correct antenna rule violations. Low current leakage is achieved as a result of the use of a fewer number of diode circuits, and the fact that they remain unconnected until used to correct an antenna rule violation.

公开(公告)号：US5977809A

公开(公告)日：1999-11-02

申请号：US968558

申请日：1997-11-12

申请人： Shyh-Jye Wang ,  Chi-Chiang Wu ,  Wen-Hsiang Huang

发明人： Shyh-Jye Wang ,  Chi-Chiang Wu ,  Wen-Hsiang Huang

IPC分类号： H03H11/16 ,  H03K5/00 ,  H03K5/13 ,  H03K5/151

CPC分类号： H03K5/1515 ,  H03K5/133 ,  H03K2005/00058

摘要： A programmable non-overlap clock generator is disclosed. This clock generator includes a primary clock signal input terminal for providing a primary clock signal, and a selection signal input terminal for providing at least one selection signal. The present invention also includes a first logic gate, whose first input terminal is coupled to receive an inverted signal of the primary clock signal. Further, the first input terminal of a second logic gate is coupled to receive the primary clock signal. A first programmable delay means, connected between an output of the first logic gate and the second input terminal of the second logic gate, is used to delay an output signal from the first logic gate a predetermined amount of time according to the selection signal. Moreover, a second programmable delay means, connected between an output of the second logic gate and the second input terminal of the first logic gate, is used to delay an output signal from the second logic gate a predetermined amount of time according to the selection signal. The programmable non-overlap clock generator therefore generates a first clock signal from the output of the first logic gate, and generates a second clock signal from the output of the second logic gate, wherein the first clock signal and the second clock signal are not logically active at the same time.

摘要翻译： 公开了可编程非重叠时钟发生器。 该时钟发生器包括用于提供主时钟信号的主时钟信号输入端和用于提供至少一个选择信号的选择信号输入端。 本发明还包括第一逻辑门，其第一输入端被耦合以接收主时钟信号的反相信号。 此外，第二逻辑门的​​第一输入端耦合以接收主时钟信号。 连接在第一逻辑门的输出和第二逻辑门的​​第二输入端之间的第一可编程延迟装置用于根据选择信号将来自第一逻辑门的输出信号延迟预定的时间量。 此外，连接在第二逻辑门的​​输出和第一逻辑门的第二输入端之间的第二可编程延迟装置用于根据选择信号将来自第二逻辑门的​​输出信号延迟预定的时间量 。 可编程非重叠时钟发生器因此从第一逻辑门的输出产生第一时钟信号，并且从第二逻辑门的​​输出产生第二时钟信号，其中第一时钟信号和第二时钟信号不是逻辑地 同时活跃。

公开(公告)号：US20060020234A1

公开(公告)日：2006-01-26

申请号：US10895358

申请日：2004-07-21

申请人： Lin-Shing Chou ,  Wen-Hsiang Huang

发明人： Lin-Shing Chou ,  Wen-Hsiang Huang

IPC分类号： A61F13/00

CPC分类号： A61F13/00063 ,  A61F2013/00217 ,  A61F2013/00255 ,  A61F2013/00285 ,  A61F2013/00536 ,  A61F2013/0054 ,  A61F2013/00846 ,  A61F2013/00863 ,  A61F2013/0091 ,  A61F2013/00927

摘要： An absorbent sac wound dressing comprising a wound-contacting layer covered with tapered pores and the bottom surface of tapered pores contacting a wound area wherein discharged exudate penetrates through, a guiding layer transmitting discharged exudate to an absorbent layer, an absorbent layer absorbing discharged exudate to make fibers expand into the shape of gel, which is effective in preventing from backflow of exudate to a wound area, and a translucent breathing layer having a broad spread of micro pores. The placement of the above layer is one on top of another in order and the peripheral edges are joined together by heat-sealing to form a sac without side escape. More particularly, the certain concentration of water-soluble antimicrobial medicines, enzymes or growth factor agents in a suitable amount are well distributed added in the absorbent layer, which is more effective in controlling a wound infection.

摘要翻译： 一种吸收囊伤口敷料，其包括覆盖有锥形孔的伤口接触层和与排出的渗出物渗透的伤口区域接触的锥形孔的底表面，将排出的渗出物渗透到吸收层的引导层，吸收排出的渗出物的吸收层 使纤维膨胀成凝胶形状，其有效地防止渗出物回流到伤口区域，以及具有广泛扩张的微孔的半透明呼吸层。 上述层的布置依次是一个在另一个之上，并且通过热封将周边边缘连接在一起以形成囊而不会侧面逃逸。 更具体地，在吸收层中加入适量的水溶性抗微生物药物，酶或生长因子试剂的一定浓度，这在抑制伤口感染方面更有效。

公开(公告)号：US07869492B2

公开(公告)日：2011-01-11

申请号：US11976285

申请日：2007-10-23

申请人： Yong Jheng Lin ,  Wen Hsiang Huang ,  Min-Yi Chen

发明人： Yong Jheng Lin ,  Wen Hsiang Huang ,  Min-Yi Chen

IPC分类号： H04B17/00

CPC分类号： H03L7/06 ,  H04L7/10

摘要： The invention proposes a simple method suitable for automatically locking frequency during USB data communication. Based on the soft plug/unplug concept proposed in the contents and the error handling mechanism defined in the USB specification, we can calibrate the clock frequency of the digitally controlled oscillator (DCO), through the token packets, to be within the acceptable frequency when USB device is attached to the host controller.

摘要翻译： 本发明提出了一种适用于在USB数据通信期间自动锁定频率的简单方法。 基于内容中提出的软插拔概念和USB规范中定义的错误处理机制，我们可以通过令牌包将数字控制振荡器（DCO）的时钟频率校准到可接受的频率范围内 USB设备连接到主机控制器。

公开(公告)号：US20080100388A1

公开(公告)日：2008-05-01

申请号：US11706199

申请日：2007-02-15

申请人： Yong Jheng Lin ,  Wen Hsiang Huang ,  Min-Yi Chen

发明人： Yong Jheng Lin ,  Wen Hsiang Huang ,  Min-Yi Chen

IPC分类号： H03L7/099 ,  G06F13/00

CPC分类号： H03L7/085 ,  H03L7/0991 ,  H03L7/181 ,  H04L7/033

摘要： A frequency-locking device including a digitally-controlled oscillator (DCO) and a comparing unit is disclosed. The DCO is used for generating an output frequency signal. The comparing unit receives a Keep Alive signal from a universal serial bus (USB) and the output frequency signal, and compares the Keep Alive signal with the output frequency signal to generate a calibration signal. Then, the DCO adjusts the frequency of the output frequency signal according to the calibration signal to meet the USB specification for data communication.

摘要翻译： 公开了一种包括数字控制振荡器（DCO）和比较单元的频率锁定装置。 DCO用于产生输出频率信号。 比较单元从通用串行总线（USB）和输出频率信号接收Keep Alive信号，并将Keep Alive信号与输出频率信号进行比较，以产生校准信号。 然后，DCO根据校准信号调整输出频率信号的频率，以符合USB规范进行数据通信。

公开(公告)号：US6034552A

公开(公告)日：2000-03-07

申请号：US70529

申请日：1998-04-30

申请人： Hun-Hsin Chang ,  Ming-Dou Ker ,  Kuo-Tsai Lee ,  Wen-Hsiang Huang

发明人： Hun-Hsin Chang ,  Ming-Dou Ker ,  Kuo-Tsai Lee ,  Wen-Hsiang Huang

IPC分类号： H01L27/02 ,  H03K19/0175 ,  H02H3/22 ,  H02H9/00 ,  H03K19/094

CPC分类号： H01L27/0251

摘要： A dynamic-floating-gate arrangement is used to improve the ESD robustness of driving-current-programmable CMOS output buffers in cell libraries, by suitably dynamically floating the gates of the NMOS/PMOS buffers using a small-dimension CMOS device having its drain connected to the gate of an unused CMOS buffer, its source connected to one of two voltage sources, and its gate connected between a resistance, that is connected between the two voltage sources, and a capacitance connected between the resistance and the same one of the two voltage sources as the source of the small-dimension CMOS device.

摘要翻译： 动态浮栅布置用于通过使用其漏极连接的小尺寸CMOS器件适当地动态地浮动NMOS / PMOS缓冲器的栅极来提高单元库中的驱动电流可编程CMOS输出缓冲器的ESD鲁棒性 到未使用的CMOS缓冲器的栅极，其源极连接到两个电压源中的一个，并且其栅极连接在连接在两个电压源之间的电阻之间，以及连接在电阻和两个电压之间的电容之间的电容 电压源作为小尺寸CMOS器件的源头。