公开(公告)号：US08313987B2

公开(公告)日：2012-11-20

申请号：US13219215

申请日：2011-08-26

申请人： Wlodek Kurjanowicz ,  Steven Smith

发明人： Wlodek Kurjanowicz ,  Steven Smith

IPC分类号： H01L21/82

CPC分类号： G11C17/16 ,  H01L23/5252 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse memory cell having a variable thickness gate dielectric. The variable thickness dielectric has a thick portion and a thin portion, where the thin portion has at least one dimension less than a minimum feature size of a process technology. The thin portion can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate dielectric substantially identical in thickness to the thick portion of the variable thickness gate dielectric of the anti-fuse transistor.

摘要翻译： 具有可变厚度栅极电介质的反熔丝存储单元。 可变厚度电介质具有厚部分和薄部分，其中薄部分具有小于工艺技术的最小特征尺寸的至少一个尺寸。 薄部分的形状可以是矩形或三角形。 反熔丝晶体管可以用于具有存取晶体管的双晶体管存储单元，栅极电介质的厚度基本上与反熔丝晶体管的可变厚度栅极电介质的厚部相同。

公开(公告)号：US07944727B2

公开(公告)日：2011-05-17

申请号：US12306114

申请日：2007-12-20

申请人： Wlodek Kurjanowicz

发明人： Wlodek Kurjanowicz

IPC分类号： G11C17/00

CPC分类号： G11C17/18 ,  G11C17/10 ,  H01L27/0203 ,  H01L27/112

摘要： A memory array having both mask programmable and one-time programmable memory cells connected to the wordlines and the bitlines. All memory cells of the memory array are configured as one-time programmable memory cells. Any number of these one-time programmable memory cells are convertible into mask programmable memory cells through mask programming, such as diffusion mask programming or contact/via mask programming. Manufacturing of such a hybrid memory array is simplified because both types of memory cells are constructed of the same materials, therefore only one common set of manufacturing process steps is required. Inadvertent user programming of the mask programmable memory cells is inhibited by a programming lock circuit.

摘要翻译： 具有连接到字线和位线的掩模可编程和一次性可编程存储器单元的存储器阵列。 存储器阵列的所有存储单元被配置为一次性可编程存储器单元。 任何数量的这些一次性可编程存储器单元通过掩模编程（例如扩散掩模编程或接触/通孔掩模编程）可转换成掩模可编程存储器单元。 这种混合存储器阵列的制造被简化，因为两种类型的存储器单元由相同的材料构成，因此仅需要一组常规的制造工艺步骤。 掩模可编程存储单元的无意的用户编程被编程锁定电路所禁止。

公开(公告)号：US07940595B2

公开(公告)日：2011-05-10

申请号：US12306940

申请日：2007-12-20

申请人： Wlodek Kurjanowicz

发明人： Wlodek Kurjanowicz

IPC分类号： G11C7/00

CPC分类号： G11C29/52 ,  G11C5/143 ,  G11C16/3454 ,  G11C16/3459 ,  G11C17/14 ,  G11C17/16 ,  G11C17/165 ,  G11C19/00 ,  G11C29/027 ,  G11C2029/0407

摘要： A power up detection system for a memory device. Two rows of memory cells are mask programmed to include a word of data having an arbitrary size. The word in the second row is a single-bit shifted version of the word in the first row, such that each bit is shifted one bit position in a predetermined direction. The bits of the first word are read from the first row into slave latches of the register stages of a data register, and then shifted into the master latches of the next register stage of the data register. The bits of the second word are read from the second row into the slave latches of the register stages. Data comparison logic compares data stored in the master and slave latches of each register stage, and provides a signal indicating matching data between the first latches and the second latches, thereby indicating successful power up of the memory device.

摘要翻译： 用于存储器件的上电检测系统。 两行存储器单元被编程为包括具有任意大小的数据字。 第二行中的字是第一行中单词的单位移位版本，使得每个位沿预定方向移位一位位置。 第一个字的位从第一行读取到数据寄存器的寄存器级的从锁存器，然后移入数据寄存器的下一个寄存器级的主锁存器。 第二个字的位从第二行读入寄存器级的从锁存器。 数据比较逻辑比较存储在每个寄存器级的主锁存器和从锁存器中的数据，并且提供指示第一锁存器和第二锁存器之间的匹配数据的信号，从而指示存储器件的成功上电。

公开(公告)号：US07764532B2

公开(公告)日：2010-07-27

申请号：US12389933

申请日：2009-02-20

申请人： Wlodek Kurjanowicz ,  Steven Smith

发明人： Wlodek Kurjanowicz ,  Steven Smith

IPC分类号： G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L21/28211 ,  H01L23/5252 ,  H01L27/10 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.

摘要翻译： 公开了一种用于非易失性存储器阵列的高速感测方案。 存储器阵列包括以互补位线配置布置的非易失性存储单元，包括用于将位线预充电到诸如VSS的第一电压电平的预充电电路，用于在补充位线对的参考位线上施加参考电荷的参考电路，以及位线 用于感测互补位线对之间的电压差的读出放大器。 当连接到激活的字线的编程的非易失性存储器单元将字线电压耦合到数据位线时，数据位线上的电压被改变。

公开(公告)号：US20080038879A1

公开(公告)日：2008-02-14

申请号：US11877229

申请日：2007-10-23

申请人： Wlodek KURJANOWICZ

发明人： Wlodek KURJANOWICZ

IPC分类号： H01L21/82

CPC分类号： H01L21/28211 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/10 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse memory cell having a variable thickness gate oxide. The variable thickness gate oxide has a thick gate oxide portion and a thin gate oxide portion, where the thing gate oxide portion has at least one dimension less than a minimum feature size of a process technology. The thin gate oxide can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate oxide substantially identical in thickness to the thick gate oxide of the variable thickness gate oxide of the anti-fuse transistor.

摘要翻译： 具有可变厚度栅极氧化物的反熔丝存储单元。 可变厚栅极氧化物具有厚的栅极氧化物部分和薄的栅极氧化物部分，其中栅极氧化物部分具有小于工艺技术的最小特征尺寸的至少一个尺寸。 薄栅氧化物的形状可以是矩形或三角形。 反熔丝晶体管可以用于具有存取晶体管的双晶体管存储单元，栅极氧化物的厚度与抗熔丝晶体管的可变厚栅极氧化物的厚栅极氧化物的厚度基本相同。

公开(公告)号：US20070165441A1

公开(公告)日：2007-07-19

申请号：US11618330

申请日：2006-12-29

申请人： Wlodek Kurjanowicz ,  Steven Smith

发明人： Wlodek Kurjanowicz ,  Steven Smith

IPC分类号： G11C7/00 ,  G11C17/00

CPC分类号： G11C17/16 ,  G11C17/18 ,  H01L21/28211 ,  H01L23/5252 ,  H01L27/10 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： A high speed sensing scheme for a non-volatile memory array is disclosed. The memory array includes non volatile memory cells arranged in a complementary bitline configuration includes precharge circuits for precharging the bitlines to a first voltage level such as VSS, a reference circuits for applying a reference charge on the reference bitlines of the complementary bitline pairs, and bitline sense amplifiers for sensing a voltage differential between the complementary bitline pairs. A voltage on the data bitline being changed when a programmed non-volatile memory cell connected to an activated wordline couples the wordline voltage to the data bitline.

摘要翻译： 公开了一种用于非易失性存储器阵列的高速感测方案。 存储器阵列包括以互补位线配置布置的非易失性存储单元，包括用于将位线预充电到诸如VSS的第一电压电平的预充电电路，用于在补充位线对的参考位线上施加参考电荷的参考电路，以及位线 用于感测互补位线对之间的电压差的读出放大器。 当连接到激活的字线的编程的非易失性存储器单元将字线电压耦合到数据位线时，数据位线上的电压被改变。

公开(公告)号：US08283751B2

公开(公告)日：2012-10-09

申请号：US12139992

申请日：2008-06-16

申请人： Wlodek Kurjanowicz

发明人： Wlodek Kurjanowicz

IPC分类号： H01L23/52

CPC分类号： H01L21/28211 ,  G11C17/16 ,  G11C17/18 ,  H01L23/5252 ,  H01L27/10 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/42384 ,  H01L29/7833 ,  H01L2924/0002 ,  H01L2924/00

摘要： Generally, the present invention provides a variable thickness gate oxide anti-fuse transistor device that can be employed in a non-volatile, one-time-programmable (OTP) memory array application. The anti-fuse transistor can be fabricated with standard CMOS technology, and is configured as a standard transistor element having a source diffusion, gate oxide, polysilicon gate and optional drain diffusion. The variable gate oxide underneath the polysilicon gate consists of a thick gate oxide region and a thin gate oxide region, where the thin gate oxide region acts as a localized breakdown voltage zone. A conductive channel between the polysilicon gate and the channel region can be formed in the localized breakdown voltage zone during a programming operation. In a memory array application, a wordline read current applied to the polysilicon gate can be sensed through a bitline connected to the source diffusion, via the channel of the anti-fuse transistor. More specifically, the present invention provides an effective method for utilizing split channel MOS structures as an anti-fuse cell suitable for OTP memories.

摘要翻译： 通常，本发明提供了一种可变厚度的栅氧化物反熔丝晶体管器件，其可以用在非易失性的一次可编程（OTP）存储器阵列应用中。 反熔丝晶体管可以用标准CMOS技术制造，并且被配置为具有源极扩散，栅极氧化物，多晶硅栅极和任选的漏极扩散的标准晶体管元件。 多晶硅栅极下面的可变栅极氧化物由厚的栅极氧化物区域和薄的栅极氧化物区域组成，其中薄的栅极氧化物区域用作局部击穿电压区域。 在编程操作期间，可以在局部击穿电压区域中形成多晶硅栅极和沟道区域之间的导电沟道。 在存储器阵列应用中，可以经由反熔丝晶体管的沟道通过连接到源极扩散的位线来感测施加到多晶硅栅极的字线读取电流。 更具体地，本发明提供了一种利用分裂沟道MOS结构作为适用于OTP存储器的反熔丝单元的有效方法。

公开(公告)号：US20120081942A1

公开(公告)日：2012-04-05

申请号：US13291520

申请日：2011-11-08

申请人： Wlodek KURJANOWICZ

发明人： Wlodek KURJANOWICZ

IPC分类号： G11C17/00

CPC分类号： G11C29/027 ,  G11C17/00 ,  G11C17/14 ,  G11C29/08 ,  G11C29/24

摘要： Test cells are included in a one-time programmable (OTP) memory array for detecting semiconductor fabrication misalignment, which can result in a potentially defective memory array. The test cells are fabricated at the same time as the normal OTP cells, except they are smaller in size along one dimension in order to detect mask misalignment along that dimension. Any fabricated test cell which cannot be programmed indicates a level of fabrication mask misalignment has occurred and the OTP memory array should not be used.

摘要翻译： 测试单元被包括在用于检测半导体制造未对准的一次性可编程（OTP）存储器阵列中，这可能导致潜在的有缺陷的存储器阵列。 测试电池与正常OTP电池同时制造，除了它们沿着一个维度的尺寸较小，以便沿着该尺寸检测掩模未对准。 任何不能编程的制造的测试单元都指示制造掩模发生不对准的水平，并且不应使用OTP存储器阵列。

公开(公告)号：US20110312169A1

公开(公告)日：2011-12-22

申请号：US13219215

申请日：2011-08-26

申请人： Wlodek KURJANOWICZ ,  Steven SMITH

发明人： Wlodek KURJANOWICZ ,  Steven SMITH

IPC分类号： H01L21/336

CPC分类号： G11C17/16 ,  H01L23/5252 ,  H01L27/101 ,  H01L27/112 ,  H01L27/11206 ,  H01L2924/0002 ,  H01L2924/00

摘要： An anti-fuse memory cell having a variable thickness gate dielectric. The variable thickness dielectric has a thick portion and a thin portion, where the thin portion has at least one dimension less than a minimum feature size of a process technology. The thin portion can be rectangular in shape or triangular in shape. The anti-fuse transistor can be used in a two-transistor memory cell having an access transistor with a gate dielectric substantially identical in thickness to the thick portion of the variable thickness gate dielectric of the anti-fuse transistor.

摘要翻译： 具有可变厚度栅极电介质的反熔丝存储单元。 可变厚度电介质具有厚部分和薄部分，其中薄部分具有小于工艺技术的最小特征尺寸的至少一个尺寸。 薄部分的形状可以是矩形或三角形。 反熔丝晶体管可以用于具有存取晶体管的双晶体管存储单元，栅极电介质的厚度基本上与反熔丝晶体管的可变厚度栅极电介质的厚部相同。

公开(公告)号：US08059479B2

公开(公告)日：2011-11-15

申请号：US12342367

申请日：2008-12-23

申请人： Wlodek Kurjanowicz

发明人： Wlodek Kurjanowicz

IPC分类号： G11C29/00

CPC分类号： G11C29/08 ,  G11C17/14 ,  G11C29/027

摘要： Circuits for testing unprogrammed OTP memories to ensure that wordline and bitline connections, column decoders, wordline drivers, correctness of decoding, sensing and multiplexing operate properly. The OTP testing system includes one or both of column test circuitry and row test circuitry. The column test circuitry charges all the bitlines to a voltage level similar to that provided by a programmed OTP memory cell during a read operation, in response to activation of a test wordline. The bitline voltages can be sensed, thereby allowing for testing of the column decoding and sense amplifier circuits. The row test circuitry charges a test bitline to a voltage level similar to that provided by a programmed OTP memory cell during a read operation, in response to activation of a wordline of the OTP memory array. This test bitline voltage can be sensed, thereby allowing for testing of the row decoding and driver circuits.

摘要翻译： 用于测试未编程的OTP存储器的电路，以确保字线和位线连接，列解码器，字线驱动器，解码，感测和复用的正确性正常工作。 OTP测试系统包括列测试电路和行测试电路中的一个或两个。 列测试电路响应于测试字线的激活，将所有位线充电到在读取操作期间与编程的OTP存储器单元提供的电压相似的电压电平。 可以检测位线电压，从而允许测试列解码和读出放大器电路。 响应于OTP存储器阵列的字线的激活，行测试电路在读操作期间将测试位线充电到类似于由编程的OTP存储器单元提供的电压电平。 可以检测该测试位线电压，从而允许测试行解码和驱动电路。