公开(公告)号：US08481380B2

公开(公告)日：2013-07-09

申请号：US12888828

申请日：2010-09-23

申请人： Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

发明人： Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

IPC分类号： H01L21/337

CPC分类号： H01L29/772 ,  G06F17/50 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/66901 ,  H01L29/808

摘要： A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce Ron. A related method and design structure are also disclosed.

摘要翻译： 提供了一种用于集成电路（IC）芯片的结栅场效应晶体管（JFET），其包括源极区，漏极区，下栅极和沟道，其中绝缘浅沟槽隔离（STI）区域从 源区域的上表面的内边缘到漏极区域的上表面的内边缘，而没有有意掺杂的区域，例如上栅极，与源极/漏极区域之间的IC芯片的上表面共面 。 此外，可以包括设置在STI区域的一部分下方的不对称的准掩埋的上栅极，但不在靠近漏极区域的STI区域的一部分下方延伸。 本发明的实施例还包括在源极区域下提供注入层以减少Ron。 还公开了相关的方法和设计结构。

公开(公告)号：US6057184A

公开(公告)日：2000-05-02

申请号：US821553

申请日：1997-03-21

申请人： Jeffrey Scott Brown ,  Stephen Scott Furkay ,  Robert John Gauthier, Jr. ,  Xiaowei Tian ,  Minh Ho Tong ,  Steven Howard Voldman

发明人： Jeffrey Scott Brown ,  Stephen Scott Furkay ,  Robert John Gauthier, Jr. ,  Xiaowei Tian ,  Minh Ho Tong ,  Steven Howard Voldman

IPC分类号： H01L21/74 ,  H01L21/8238 ,  H01L27/092

CPC分类号： H01L21/823892 ,  H01L21/743 ,  H01L27/0928

摘要： A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within the epitaxial layer above the buried p+ blanket layer implant. In one exemplary embodiment, the device includes a shallow P-well with the P+ connecting implant in a position within the epitaxial layer connecting the shallow P-well and the buried P+ blanket implant layer.

摘要翻译： 一种用于这种器件的半导体器件和制造方法，其中P-外延层位于P ++衬底之上。 P ++掩埋层植入物位于P ++衬底和P-外延层之间的器件内。 将连接的p +植入物放置在掩埋的p +覆盖层植入物上方的外延层内。 在一个示例性实施例中，该器件包括浅P阱，其中P +连接植入物位于连接浅P阱和掩埋P +覆盖植入层的外延层内的位置。

公开(公告)号：US20120074469A1

公开(公告)日：2012-03-29

申请号：US12888828

申请日：2010-09-23

申请人： Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

发明人： Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

IPC分类号： H01L29/80 ,  G06F17/50 ,  H01L21/337

CPC分类号： H01L29/772 ,  G06F17/50 ,  H01L29/0649 ,  H01L29/0843 ,  H01L29/1066 ,  H01L29/66901 ,  H01L29/808

摘要： A junction gate field-effect transistor (JFET) for an integrated circuit (IC) chip is provided comprising a source region, a drain region, a lower gate, and a channel, with an insulating shallow trench isolation (STI) region extending from an inner edge of an upper surface of the source region to an inner edge of an upper surface of the drain region, without an intentionally doped region, e.g., an upper gate, coplanar with an upper surface of the IC chip between the source/drain regions. In addition, an asymmetrical quasi-buried upper gate can be included, disposed under a portion of the STI region, but not extending under a portion of the STI region proximate to the drain region. Embodiments of this invention also include providing an implantation layer, under the source region, to reduce Ron. A related method and design structure are also disclosed.

摘要翻译： 提供了一种用于集成电路（IC）芯片的结栅场效应晶体管（JFET），其包括源极区，漏极区，下栅极和沟道，其中绝缘浅沟槽隔离（STI）区域从 源区域的上表面的内边缘到漏极区域的上表面的内边缘，而没有有意掺杂的区域，例如上栅极，与源极/漏极区域之间的IC芯片的上表面共面 。 此外，可以包括设置在STI区域的一部分下方的不对称的准掩埋的上栅极，但不在靠近漏极区域的STI区域的一部分下方延伸。 本发明的实施例还包括在源极区域下提供注入层以减少Ron。 还公开了相关的方法和设计结构。

公开(公告)号：US6100153A

公开(公告)日：2000-08-08

申请号：US8875

申请日：1998-01-20

申请人： Edward J. Nowak ,  Xiaowei Tian ,  Minh H. Tong

发明人： Edward J. Nowak ,  Xiaowei Tian ,  Minh H. Tong

IPC分类号： H01L27/04 ,  H01L21/329 ,  H01L21/334 ,  H01L21/822 ,  H01L21/8234 ,  H01L27/06 ,  H01L27/108 ,  H01L29/94 ,  H01L21/20

CPC分类号： H01L29/66166 ,  H01L29/66181

摘要： A diffusion resistor is provided that utilizes the block mask to cover only the intrinsic polysilicon gate region. The n-type source/drain doping is implanted in the contact regions, but not in the intrinsic polysilicon gate region. A N-type (or P-type) diffusion resistor in P-well (or N-well) is provided that utilizes a block mask to cover only the intrinsic polysilicon gate region. The N-type (or P-type) source/drain doping is implanted in the contact regions but not in the intrinsic polysilicon gate region. The P-well (or N-well) block mask is used to keep the P-well (or N-well) from forming under the buried resistor. This makes the parasitic capacitance of the diffusion junction very low. Also provided is a buried capacitor and method of making both a buried resistor and a buried capacitor.

摘要翻译： 提供了扩散电阻器，其利用块掩模仅覆盖本征多晶硅栅极区域。 n型源极/漏极掺杂注入到接触区域中，但不注入本征多晶硅栅极区域。 提供了P阱（或N阱）中的N型（或P型）扩散电阻器，其利用块掩模仅覆盖本征多晶硅栅极区域。 N型（或P型）源极/漏极掺杂注入到接触区域中，但不注入本征多晶硅栅极区域。 P阱（或N阱）块掩模用于保持P阱（或N阱）在埋电阻下形成。 这使得扩散结的寄生电容非常低。 还提供了埋入电容器和制造埋电阻器和埋入电容器的方法。

公开(公告)号：US6097068A

公开(公告)日：2000-08-01

申请号：US10870

申请日：1998-01-22

申请人： Jeffrey Scott Brown ,  Stephen Scott Furkay ,  Robert John Gauthier, Jr. ,  Xiaowei Tian ,  Minh Ho Tong ,  Steven Howard Voldman

发明人： Jeffrey Scott Brown ,  Stephen Scott Furkay ,  Robert John Gauthier, Jr. ,  Xiaowei Tian ,  Minh Ho Tong ,  Steven Howard Voldman

IPC分类号： H01L21/74 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/76

CPC分类号： H01L21/823892 ,  H01L21/743 ,  H01L27/0928

摘要： A semiconductor device and method of fabrication for such device in which a P- epitaxial layer is positioned above a P++ substrate. A P++ buried layer implant is positioned within the device between the P++ substrate and the P- epitaxial layer. A connecting p+ implant is placed within the epitaxial layer above the buried p+ blanket layer implant. In one exemplary embodiment, the device includes a shallow P-well with the P+ connecting implant in a position within the epitaxial layer connecting the shallow P-well and the buried P+ blanket implant layer.

摘要翻译： 一种用于这种器件的半导体器件和制造方法，其中P-外延层位于P ++衬底之上。 P ++掩埋层植入物位于P ++衬底和P-外延层之间的器件内。 将连接的p +植入物放置在掩埋的p +覆盖层植入物上方的外延层内。 在一个示例性实施例中，该器件包括浅P阱，其中P +连接植入物位于连接浅P阱和掩埋P +覆盖植入层的外延层内的位置。

公开(公告)号：US5972745A

公开(公告)日：1999-10-26

申请号：US866674

申请日：1997-05-30

申请人： Howard L. Kalter ,  Edward J. Nowak ,  Xiaowei Tian ,  Minh H. Tong ,  William R. Tonti

发明人： Howard L. Kalter ,  Edward J. Nowak ,  Xiaowei Tian ,  Minh H. Tong ,  William R. Tonti

IPC分类号： H01L21/265 ,  H01L21/761 ,  H01L21/8238

CPC分类号： H01L21/823892 ,  H01L21/761 ,  H01L21/26586

摘要： A method of forming a self-aligned halo-isolated well with a single mask is disclosed. First, a layer of resist is disposed over at least a portion of a substrate's surface. Then, an impurity of a first polarity type is implanted at an angle into the substrate through a gap in the layer of resist, thus forming a well having the impurity of the first polarity, which extends beneath the layer of resist. An impurity of a second polarity type is also implanted, using the same mask as previously used. The second implantation forms a well of the impurity of the second polarity disposed within the well of to impurity of the first polarity.

摘要翻译： 公开了一种用单一掩模形成自对准卤素隔离井的方法。 首先，将抗蚀剂层设置在衬底表面的至少一部分上。 然后，第一极性类型的杂质通过抗蚀剂层中的间隙以一定角度注入到衬底中，从而形成具有在抗蚀剂层下方延伸的具有第一极性杂质的阱。 使用与以前使用的相同的掩模也植入第二极性类型的杂质。 第二次注入形成设置在第一极性杂质的阱内的第二极性杂质的阱。

公开(公告)号：US5883566A

公开(公告)日：1999-03-16

申请号：US804601

申请日：1997-02-24

申请人： Edward J. Nowak ,  Xiaowei Tian ,  Minh H. Tong

发明人： Edward J. Nowak ,  Xiaowei Tian ,  Minh H. Tong

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L29/8605 ,  H01C1/02

CPC分类号： H01L29/8605

摘要： A noise-isolated buried resistor satisfies the requirements for low-noise analog designs requiring well controlled ohmic resistors. A field shield is provided between the buried resistor and the substrate to isolate the buried resistor from the substrate noise. This is accomplished by using the standard buried resistor layout and mask sequence with two exceptions. First, the buried resistor is placed in an N-well region, rather than simply a P-well region. Second, a boron implant is added through the buried resistor mask to provide a P-well inside the N-well to isolate the buried resistor electrically from the N-well. The N-well may then be electrically connected to a "quiet" ground. The P-well inside of the N-well may be left floating.

摘要翻译： 隔离噪声的电阻器满足要求良好控制的欧姆电阻器的低噪声模拟设计的要求。 在掩埋电阻和衬底之间提供场屏蔽，以将掩埋电阻与衬底噪声隔离。 这是通过使用标准埋入电阻器布局和掩模序列来实现的，有两个例外。 首先，埋电阻器放置在N阱区域中，而不是简单的P阱区域。 第二，通过埋入电阻掩模添加硼注入，以在N阱内提供P阱以将掩埋电阻器与N阱电隔离。 然后，N阱可以电连接到“安静”的地面。 N井内的P井可以悬空。

公开(公告)号：USD1036532S1

公开(公告)日：2024-07-23

申请号：US29873360

申请日：2023-03-30

申请人： Xiaowei Tian

设计人： Xiaowei Tian

摘要： FIG. 1 is a front, left and bottom perspective view of a surveillance camera, showing my new design;
FIG. 2 is a rear, right and top perspective view thereof;
FIG. 3 is a front view thereof;
FIG. 4 is a rear view thereof;
FIG. 5 is a left side view thereof;
FIG. 6 is a right side view thereof;
FIG. 7 is a top plan view thereof; and,
FIG. 8 is a bottom plan view thereof.
The broken lines shown in the drawings illustrate portions of the surveillance camera that form no part of the claimed design.

公开(公告)号：US08754455B2

公开(公告)日：2014-06-17

申请号：US12983489

申请日：2011-01-03

申请人： Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

发明人： Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

IPC分类号： H01L29/80

CPC分类号： H01L29/66916 ,  H01L27/14679 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/808 ,  H01L29/8086

摘要： Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.

摘要翻译： 公开了具有一个或多个P型硅锗（SiGe）或硅碳化硅（SiGeC）栅极（即，SiGe或SiGeC基异质结JFET）的结型场效应晶体管（JFET）结构的实施例。 P型SiGe或SiGeC栅极允许较低的截止电压（即，较低的Voff），而不增加导通电阻（Ron）。 具体来说，P型栅极中的SiGe或SiGeC材料限制了P型掺杂物的扩散，从而确保了P型栅极与N型沟道区域结的关系更明确（即，与分级相反的突发性 ）。 通过明确定义该结，N型沟道区中的耗尽层延伸。 延伸耗尽层依次允许更快的夹断（即，需要更低的Voff）。 P型SiGe或SiGeC栅极可以结合到常规的横向JFET结构和/或垂直JFET结构中。 本文还公开了形成这种JFET结构的方法的实施例。

公开(公告)号：US20120168820A1

公开(公告)日：2012-07-05

申请号：US12983489

申请日：2011-01-03

申请人： Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

发明人： Xuefeng Liu ,  Richard A. Phelps ,  Robert M. Rassel ,  Xiaowei Tian

IPC分类号： H01L29/80 ,  H01L21/335

CPC分类号： H01L29/66916 ,  H01L27/14679 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/42316 ,  H01L29/66462 ,  H01L29/808 ,  H01L29/8086

摘要： Disclosed are embodiments of a junction field effect transistor (JFET) structure with one or more P-type silicon germanium (SiGe) or silicon germanium carbide (SiGeC) gates (i.e., a SiGe or SiGeC based heterojunction JFET). The P-type SiGe or SiGeC gate(s) allow for a lower pinch off voltage (i.e., lower Voff) without increasing the on resistance (Ron). Specifically, SiGe or SiGeC material in a P-type gate limits P-type dopant out diffusion and, thereby ensures that the P-type gate-to-N-type channel region junction is more clearly defined (i.e., abrupt as opposed to graded). By clearly defining this junction, the depletion layer in the N-type channel region is extended. Extending the depletion layer in turn allows for a faster pinch off (i.e., requires lower Voff). P-type SiGe or SiGeC gate(s) can be incorporated into conventional lateral JFET structures and/or vertical JFET structures. Also disclosed herein are embodiments of a method of forming such a JFET structure.

摘要翻译： 公开了具有一个或多个P型硅锗（SiGe）或硅碳化硅（SiGeC）栅极（即，SiGe或SiGeC基异质结JFET）的结型场效应晶体管（JFET）结构的实施例。 P型SiGe或SiGeC栅极允许较低的截止电压（即，较低的Voff），而不增加导通电阻（Ron）。 具体来说，P型栅极中的SiGe或SiGeC材料限制了P型掺杂物的扩散，从而确保了P型栅极与N型沟道区域结的关系更明确（即，与分级相反的突发性 ）。 通过明确定义该结，N型沟道区中的耗尽层延伸。 延伸耗尽层依次允许更快的夹断（即，需要更低的Voff）。 P型SiGe或SiGeC栅极可以结合到常规的横向JFET结构和/或垂直JFET结构中。 本文还公开了形成这种JFET结构的方法的实施例。