公开(公告)号：US20140021534A1

公开(公告)日：2014-01-23

申请号：US13552607

申请日：2012-07-18

申请人： Purakh Raj VERMA ,  Liang YI ,  Yemin DONG

发明人： Purakh Raj VERMA ,  Liang YI ,  Yemin DONG

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/82385 ,  H01L29/0878 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66689 ,  H01L29/66704 ,  H01L29/7825

摘要： A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having an upper and a lower portion is formed in a trench in the substrate in the device region. The upper portion forms a gate electrode and the lower portion forms a gate field plate. First and second surface doped regions are formed adjacent to the gate. The gate field plate introduces vertical reduced surface (RESURF) effect in a drift region of the device.

摘要翻译： 公开了一种形成装置的方法。 提供了用设备区域定义的衬底。 具有上部和下部的栅极形成在器件区域中的衬底中的沟槽中。 上部形成栅电极，下部形成栅极场板。 第一和第二表面掺杂区域邻近栅极形成。 栅极场板在器件的漂移区域中引入垂直缩小表面（RESURF）效应。

公开(公告)号：US08999769B2

公开(公告)日：2015-04-07

申请号：US13552607

申请日：2012-07-18

申请人： Purakh Raj Verma ,  Liang Yi ,  Yemin Dong

发明人： Purakh Raj Verma ,  Liang Yi ,  Yemin Dong

IPC分类号： H01L21/332 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78 ,  H01L29/08 ,  H01L29/423 ,  H01L29/51

CPC分类号： H01L21/82385 ,  H01L29/0878 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66689 ,  H01L29/66704 ,  H01L29/7825

摘要： A method of forming a device is disclosed. A substrate defined with a device region is provided. A gate having an upper and a lower portion is formed in a trench in the substrate in the device region. The upper portion forms a gate electrode and the lower portion forms a gate field plate. First and second surface doped regions are formed adjacent to the gate. The gate field plate introduces vertical reduced surface (RESURF) effect in a drift region of the device.

摘要翻译： 公开了一种形成装置的方法。 提供了用设备区域定义的衬底。 具有上部和下部的栅极形成在器件区域中的衬底中的沟槽中。 上部形成栅电极，下部形成栅极场板。 第一和第二表面掺杂区域邻近栅极形成。 栅极场板在器件的漂移区域中引入垂直缩小表面（RESURF）效应。

公开(公告)号：US20100320529A1

公开(公告)日：2010-12-23

申请号：US12488451

申请日：2009-06-19

申请人： Yemin Dong ,  Purakh Raj Verma ,  Xin Zou ,  Chao Cheng ,  Shao-fu Sanford Chu

发明人： Yemin Dong ,  Purakh Raj Verma ,  Xin Zou ,  Chao Cheng ,  Shao-fu Sanford Chu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/1041 ,  H01L29/4238

摘要： A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor.

摘要翻译： 一种集成电路系统的制造方法，包括：提供具有活性区域的半导体衬底，以第一浓度注入第一类型的杂质; 在活性区周围形成隔离区; 通过在有源区域和隔离区域上施加注入第二种类型的杂质的第二种浓度的栅电极来形成寄生晶体管; 以及施加隔离边缘注入，其中第一类型的杂质具有大于或等于第二浓度的第三浓度，用于抑制寄生晶体管。

公开(公告)号：US08138051B2

公开(公告)日：2012-03-20

申请号：US12488451

申请日：2009-06-19

申请人： Yemin Dong ,  Purakh Raj Verma ,  Xin Zou ,  Chao Cheng ,  Shao-fu Sanford Chu

发明人： Yemin Dong ,  Purakh Raj Verma ,  Xin Zou ,  Chao Cheng ,  Shao-fu Sanford Chu

IPC分类号： H01L21/336 ,  H01L29/94 ,  H01L29/76 ,  H01L31/119 ,  H01L29/78

CPC分类号： H01L21/76224 ,  H01L21/76232 ,  H01L21/823481 ,  H01L21/823878 ,  H01L29/1041 ,  H01L29/4238

摘要： A method of manufacture of an integrated circuit system includes: providing a semiconductor substrate having an active region, implanted with impurities of a first type at a first concentration; forming an isolation region around the active region; forming a parasitic transistor by applying a gate electrode, implanted with impurities of a second type at a second concentration, over the active region and the isolation region; and applying an isolation edge implant, with the impurities of the first type at a third concentration greater than or equal to the second concentration, for suppressing the parasitic transistor.

摘要翻译： 一种集成电路系统的制造方法，包括：提供具有活性区域的半导体衬底，以第一浓度注入第一类型的杂质; 在活性区周围形成隔离区; 通过在有源区域和隔离区域上施加注入第二种类型的杂质的第二种浓度的栅电极来形成寄生晶体管; 以及施加隔离边缘注入，其中第一类型的杂质具有大于或等于第二浓度的第三浓度，用于抑制寄生晶体管。