公开(公告)号：US20070161134A1

公开(公告)日：2007-07-12

申请号：US11370062

申请日：2006-03-08

申请人： Ching-Fuh Lin ,  Kuo-Jui Sun ,  Ping-Hung Shih ,  Yi-Shin Su

发明人： Ching-Fuh Lin ,  Kuo-Jui Sun ,  Ping-Hung Shih ,  Yi-Shin Su

IPC分类号： H01L21/00

CPC分类号： H01S3/169 ,  H01S3/163 ,  H01S5/021

摘要： A method of using nanoparticles to fabricate an emitting layer of an optical communication light source on a substrate is proposed, in which a host capable of reacting with unstable ions on the surface of a rare earth ions nanomaterial is used as a carrier of nanoparticles to make the rare earth ions nanomaterial release rare earth ions, thereby forming an emitting layer that can be excited by an external current or light source to emit light.

摘要翻译： 提出了一种使用纳米粒子制造光通信光源在衬底上的发光层的方法，其中使用能够与稀土离子纳米材料表面上的不稳定离子反应的主体作为纳米粒子的载体， 稀土离子纳米材料释放稀土离子，从而形成可由外部电流或光源激发发光的发光层。

公开(公告)号：US20060044718A1

公开(公告)日：2006-03-02

申请号：US10933181

申请日：2004-09-02

申请人： Shin Su ,  Chun-Hsiang Lai ,  Cha-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Shin Su ,  Chun-Hsiang Lai ,  Cha-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H02H9/00

CPC分类号： H01L27/0251 ,  H01L27/0292

摘要： A device for connection between supply buses in mixed power integrated circuits includes a diode in series with a transistor with an active p-ring in a semiconductor substrate. The active p-ring surrounds the source and drain of the transistor with a conductive region having the same conductivity type as the semiconductor substrate. A control circuit coupled to the p-ring applies a bias voltage in response to an ESD event affecting the first and second conductors. The bias voltage tends to inject carriers into the semiconductor substrate which enables discharge of the short voltage pulse via a parasitic SCR in the substrate from the anode of the diode to the source of the transistor.

摘要翻译： 用于在混合功率集成电路中的电源总线之间连接的装置包括与在半导体衬底中具有有源p型环的晶体管串联的二极管。 有源P环围绕具有与半导体衬底相同导电类型的导电区域的晶体管的源极和漏极。 耦合到p型环的控制电路响应于影响第一和第二导体的ESD事件施加偏置电压。 偏置电压倾向于将载流子注入到半导体衬底中，其能够通过衬底中的寄生SCR从二极管的阳极到晶体管的源极放电短电压脉冲。

公开(公告)号：US06947267B2

公开(公告)日：2005-09-20

申请号：US09853591

申请日：2001-05-14

申请人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Tao-Cheng Lu

发明人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Tao-Cheng Lu

IPC分类号： H01L27/02 ,  H02H3/22

CPC分类号： H01L27/0292 ,  H01L27/0285

摘要： The present invention relates an electrostatic discharge (ESD) protection device that is applied to a mixed voltage circuit assembly. The device comprises a RC controlled circuit subassembly and a field transistor, which the RC controlled circuit is coupled with the mixed voltage circuit assembly to substantially control the ESD protection device to be ON or OFF. The field transistor is coupled between a first power supply and a second power supply of said mixed voltage circuit assembly, which is off on the condition of a normal operating condition and is conducting as an ESD event occurred.

摘要翻译： 本发明涉及一种应用于混合电压电路组件的静电放电（ESD）保护装置。 该装置包括RC控制电路子组件和场晶体管，RC控制电路与混合电压电路组件耦合，以基本上控制ESD保护装置的导通或截止。 场晶体管耦合在所述混合电压电路组件的第一电源和第二电源之间，所述第二电源在正常工作条件下处于关断状态，并且当ESD事件发生时导通。

公开(公告)号：US06933540B2

公开(公告)日：2005-08-23

申请号：US10606922

申请日：2003-06-27

申请人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Tao-Cheng Lu

发明人： Meng-Huang Liu ,  Chun-Hsiang Lai ,  Shin Su ,  Tao-Cheng Lu

IPC分类号： H01L27/02 ,  H01L29/72

CPC分类号： H01L27/0262 ,  H01L29/87

摘要： An ESD protection apparatus for dual-polarity input pad comprises a triple-well formed with a first, second and third regions to form an SCR structure. A first and second ground connection regions of opposite conductivity types are formed on the first region, a first and second input connection regions of opposite conductivity types are formed in the third region, and a bridge region is formed across the second region and extends to the first and third regions. Under normal operation, the first, second, and third regions form two back-to-back diodes. Under positive polarity ESD event, breakdown is occurred between the bridge and first regions to thereby trigger an SCR circuit for positive polarity ESD protection. Under negative polarity ESD event, breakdown is occurred between the bridge and third regions to thereby trigger an SCR circuit for negative polarity ESD protection.

摘要翻译： 用于双极性输入焊盘的ESD保护装置包括形成有第一，第二和第三区域以形成SCR结构的三阱。 在第一区域上形成有相反导电类型的第一和第二接地连接区域，在第三区域中形成相反导电类型的第一和第二输入连接区域，跨越第二区域形成桥接区域并延伸到 第一和第三区域。 在正常操作下，第一，第二和第三区域形成两个背对背二极管。 在正极性ESD事件下，在桥与第一区之间发生击穿，从而触发用于正极性ESD保护的SCR电路。 在负极性ESD事件下，桥和第三区之间发生击穿，从而触发用于负极性ESD保护的SCR电路。

公开(公告)号：US08735555B2

公开(公告)日：2014-05-27

申请号：US12297418

申请日：2007-04-16

申请人： John Clark Lagarias ,  Yi-Shin Su

发明人： John Clark Lagarias ,  Yi-Shin Su

IPC分类号： C07K14/415

CPC分类号： C12N15/8261 ,  C07K14/415 ,  C12N15/8209 ,  Y02A40/146

摘要： This invention pertains to the discovery of mutant phytochromes that when introduced into a plant alter the photomorphogenic properties of that plant. In certain embodiments transfection of plants by nucleic acid constructs expressing the mutant phytochromes produced plants having a phenotype characterized by light-independent activation. Thus, in certain embodiments, this invention provides a transgenic plant or plant cell comprising a mutant phytochrome where the mutant phytochrome is a light-stable phytochrome; and the transgenic plant shows decreased shade avoidance as compared to the same species or strain of plant lacking the mutant phytochrome. In various embodiments the mutant phytochrome comprises a mutation at the position corresponding to tyrosine residue 276 in an Arabidopsis phytochrome where the mutation is to a residue other than tyrosine.

摘要翻译： 本发明涉及突变体植物色素的发现，当植物被引入植物变种时，该植物色素改变该植物的光形态发生性质。 在某些实施方案中，通过表达突变体植物色素的核酸构建体转染植物产生具有以光独立活化为特征的表型的植物。 因此，在某些实施方案中，本发明提供了包含突变体植物色素的转基因植物或植物细胞，其中突变体植物色素是光稳定的植物色素; 与缺乏突变体植物色素的植物相同的物种或株系相比，转基因植物显示出减少的避光。 在各种实施方案中，突变体植物色素在拟南芥植物色素中的对应于酪氨酸残基276的位置处包含突变，其中突变为除酪氨酸以外的残基。

公开(公告)号：US07829408B2

公开(公告)日：2010-11-09

申请号：US12429951

申请日：2009-04-24

申请人： Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

发明人： Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

IPC分类号： H01L21/8238

CPC分类号： H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.

摘要翻译： 本发明公开了一种横向双扩散金属氧化物半导体晶体管（LDMOS）及其制造方法。 LDMOS包括衬底，第一阱，漏极，第二阱和源极。 衬底包括第一导电掺杂剂。 第一阱包括第二导电掺杂剂并形成在衬底的一部分中，并且漏极位于第一阱中。 第二阱包括第一导电掺杂剂并且形成在衬底的另一部分中，并且源位于第二阱中。 源包括从衬底的顶表面向下延伸的轻掺杂区域和重掺杂区域。 轻掺杂区域的深度大于重掺杂区域的深度。

公开(公告)号：US20090209075A1

公开(公告)日：2009-08-20

申请号：US12429951

申请日：2009-04-24

申请人： Cheng-Chi LIN ,  Shin Su ,  Chein-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

发明人： Cheng-Chi LIN ,  Shin Su ,  Chein-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

IPC分类号： H01L21/336

CPC分类号： H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.

摘要翻译： 本发明公开了一种横向双扩散金属氧化物半导体晶体管（LDMOS）及其制造方法。 LDMOS包括衬底，第一阱，漏极，第二阱和源极。 衬底包括第一导电掺杂剂。 第一阱包括第二导电掺杂剂并形成在衬底的一部分中，并且漏极位于第一阱中。 第二阱包括第一导电掺杂剂并且形成在衬底的另一部分中，并且源位于第二阱中。 源包括从衬底的顶表面向下延伸的轻掺杂区域和重掺杂区域。 轻掺杂区域的深度大于重掺杂区域的深度。

公开(公告)号：US07525153B2

公开(公告)日：2009-04-28

申请号：US11399427

申请日：2006-04-07

申请人： Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

发明人： Cheng-Chi Lin ,  Shin Su ,  Chien-Wen Chu ,  Shih-Chin Lien ,  Chin-Pen Yeh

IPC分类号： H01L29/94

CPC分类号： H01L29/0847 ,  H01L29/086 ,  H01L29/0878 ,  H01L29/42368 ,  H01L29/4933 ,  H01L29/66659 ,  H01L29/7816 ,  H01L29/7835

摘要： The present invention discloses a laterally double-diffused metal oxide semiconductor transistor (LDMOS) and a method for fabricating the same. The LDMOS includes a substrate, a first well, a drain, a second well and a source. The substrate includes a first conductive dopant. The first well includes a second conductive dopant and formed in a part of the substrate, and the drain is located in the first well. The second well includes the first conductive dopant and formed in another part of the substrate, and the source located in the second well. The source includes a lightly doped region and a heavily doped region extending downwardly from a top surface of the substrate. The depth of the lightly doped region is more than the depth of the heavily doped region.

摘要翻译： 本发明公开了一种横向双扩散金属氧化物半导体晶体管（LDMOS）及其制造方法。 LDMOS包括衬底，第一阱，漏极，第二阱和源极。 衬底包括第一导电掺杂剂。 第一阱包括第二导电掺杂剂并形成在衬底的一部分中，并且漏极位于第一阱中。 第二阱包括第一导电掺杂剂并且形成在衬底的另一部分中，并且源位于第二阱中。 源包括从衬底的顶表面向下延伸的轻掺杂区域和重掺杂区域。 轻掺杂区域的深度大于重掺杂区域的深度。

公开(公告)号：US07291870B2

公开(公告)日：2007-11-06

申请号：US10904475

申请日：2004-11-12

申请人： Chun-Hsiang Lai ,  Shin Su ,  Chia-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Chun-Hsiang Lai ,  Shin Su ,  Chia-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H01L29/72

CPC分类号： H01L27/0266 ,  H01L29/7436 ,  H01L29/87

摘要： An electrostatic discharge (ESD) protection circuit coupled to an input pad comprises a diode formed in a substrate and coupled to the input pad; a P deep well formed in the substrate; an N well formed in the P deep well; a first P+ doped region in the N well; and an NMOS transistor formed on the substrate, comprising a gate, a source and a drain, wherein the drain is formed in the N well and coupled to a Vcc, and the source is formed in the P deep well; and a second P+ doped region formed in the P deep well. The ESD protection circuit uses a smaller area than the conventional ESD protection circuit.

摘要翻译： 耦合到输入焊盘的静电放电（ESD）保护电路包括形成在衬底中并耦合到输入焊盘的二极管; 在衬底中形成的P阱; 在P深井中形成N井; N阱中的第一P +掺杂区; 以及形成在所述衬底上的NMOS晶体管，包括栅极，源极和漏极，其中所述漏极形成在所述N阱中并耦合到Vcc，并且所述源极形成在所述P阱中; 以及形成在P深井中的第二P +掺杂区域。 ESD保护电路使用比常规ESD保护电路更小的面积。

公开(公告)号：US07187527B2

公开(公告)日：2007-03-06

申请号：US10933181

申请日：2004-09-02

申请人： Shin Su ,  Chun-Hsiang Lai ,  Cha-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

发明人： Shin Su ,  Chun-Hsiang Lai ,  Cha-Ling Lu ,  Yen-Hung Yeh ,  Tao-Cheng Lu

IPC分类号： H02H9/00

CPC分类号： H01L27/0251 ,  H01L27/0292

摘要： A device for connection between supply buses in mixed power integrated circuits includes a diode in series with a transistor with an active p-ring in a semiconductor substrate. The active p-ring surrounds the source and drain of the transistor with a conductive region having the same conductivity type as the semiconductor substrate. A control circuit coupled to the p-ring applies a bias voltage in response to an ESD event affecting the first and second conductors. The bias voltage tends to inject carriers into the semiconductor substrate which enables discharge of the short voltage pulse via a parasitic SCR in the substrate from the anode of the diode to the source of the transistor.

摘要翻译： 用于在混合功率集成电路中的电源总线之间连接的装置包括与在半导体衬底中具有有源p型环的晶体管串联的二极管。 有源P环围绕具有与半导体衬底相同的导电类型的导电区域的晶体管的源极和漏极。 耦合到p型环的控制电路响应于影响第一和第二导体的ESD事件施加偏置电压。 偏置电压倾向于将载流子注入到半导体衬底中，其能够通过衬底中的寄生SCR从二极管的阳极到晶体管的源极放电短电压脉冲。