公开(公告)号：US6081159A

公开(公告)日：2000-06-27

申请号：US164358

申请日：1998-10-01

Applicant: Chung Hwan Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu ,  Yeong Cheol Hyeon ,  Min Park

Inventor： Chung Hwan Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu ,  Yeong Cheol Hyeon ,  Min Park

IPC: H04B1/62 ,  H03F1/32 ,  H03F1/26

CPC classification number: H03F1/342 ,  H03F1/3205

Abstract: An apparatus for improving linearity of small signal according to the present invention comprises a least of one non-linear signal generating means for receiving a first DC bias larger than a threshold voltage and for generating a non-linear signal; feedback means for returning the non-linear signal from said a least of one non-linear signal generating means; and amplifying means for receiving, amplifying and outputting to an output unit, a second DC bias larger than the threshold voltage and a reversed and feedback non-linear signal such that the non-linear signal is cancelled. The linearizers according to the present invention have a higher linearity and a simple constitution, and thereby being used for various terminals.

Abstract translation: 根据本发明的用于提高小信号线性度的装置包括至少一个非线性信号发生装置，用于接收大于阈值电压的第一DC偏压并用于产生非线性信号; 用于从所述至少一个非线性信号产生装置返回非线性信号的反馈装置; 以及放大装置，用于对输出单元接收，放大和输出大于阈值电压的第二DC偏置和反相和反馈非线性信号，使得非线性信号被消除。 根据本发明的线性化器具有较高的线性度和简单的结构，从而用于各种端子。

公开(公告)号：US5964629A

公开(公告)日：1999-10-12

申请号：US754804

申请日：1996-11-21

Applicant: Jong Moon Park ,  Jin Keon Ku ,  Ki Hong Kim ,  Yeong Cheol Hyeon ,  Min Park

Inventor： Jong Moon Park ,  Jin Keon Ku ,  Ki Hong Kim ,  Yeong Cheol Hyeon ,  Min Park

IPC: H01J31/15 ,  H01J9/02

CPC classification number: H01J9/025

Abstract: To form a silicon tip having an undercut, a photoresist pattern having a vertical profile or a positive profile is formed on a silicon substrate and an under-cuted isotropic etching process is then performed using the photoresist pattern as a mask. First and second insulation films are formed on the silicon tip and the silicon substrate except for the silicon tip. The first insulation film is then separated from the second insulation film.

Abstract translation: 为了形成具有底切的硅尖端，在硅衬底上形成具有垂直轮廓或正轮廓的光致抗蚀剂图案，然后使用光致抗蚀剂图案作为掩模进行下切各向同性蚀刻工艺。 第一和第二绝缘膜形成在除硅尖端之外的硅尖端和硅衬底上。 然后将第一绝缘膜与第二绝缘膜分离。

公开(公告)号：US5840609A

公开(公告)日：1998-11-24

申请号：US951564

申请日：1997-10-16

Applicant: Yeong Cheol Hyeon ,  Hyun Kyu Yu

Inventor： Yeong Cheol Hyeon ,  Hyun Kyu Yu

IPC: H01L21/28 ,  H01L21/3105 ,  H01L21/336 ,  H01L29/49 ,  H01L21/26

CPC classification number: H01L29/6659 ,  H01L21/31051 ,  H01L29/4925 ,  H01L29/66545

Abstract: A method for manufacturing a semiconductor device having a stacked gate electrode structure of self-aligned polysilicon-metal, which is capable of minimizing the variation in structural and electrical characteristics of the gate electrode, while utilizing the manufacturing process of forming a conventional silicone semiconductor memory device, is disclosed. According to the method for manufacturing a semiconductor device of the present invention, the conventional technique generally used in the manufacturing process of forming the silicon semiconductor device can be effectively utilized. Further, an excessive etch loss in the oxide layer can be restrained by using the oxide spacer of the self-aligned oxide layer in forming the metal layer at the gate electrode structure. Furthermore, it has an advantageous effect that the stable electrical characteristics of the resulting device can be obtained by using the polysilicon layer as a basic constituting material of the gate electrode thereof.

Abstract translation: 一种用于制造具有自对准多晶硅 - 金属堆叠栅电极结构的半导体器件的方法，其能够最小化栅电极的结构和电特性的变化，同时利用形成常规硅氧烷半导体存储器的制造工艺 设备。 根据本发明的半导体器件的制造方法，可以有效地利用通常用于形成硅半导体器件的制造工艺中的常规技术。 此外，通过在栅极电极结构形成金属层时，通过使用自对准氧化物层的氧化物间隔物，可以抑制氧化物层中的过度的蚀刻损失。 此外，通过使用多晶硅层作为其栅电极的基本构成材料，可以获得所得到的器件的稳定电特性。

公开(公告)号：US5769679A

公开(公告)日：1998-06-23

申请号：US710528

申请日：1996-09-18

Applicant: Jong-Moon Park ,  Yeong-Cheol Hyeon ,  Kee-Soo Nam

Inventor： Jong-Moon Park ,  Yeong-Cheol Hyeon ,  Kee-Soo Nam

IPC: H01J17/49 ,  H01J9/02 ,  H01J1/30 ,  H01J9/18

CPC classification number: H01J9/025 ,  H01J2201/30423

Abstract: In a method, a film for a gate electrode, exposed through the sidewall of a trench, is thermally treated to grow a thermal oxide film which is, then, removed at the lateral side of the gate electrode, to spatially separate the gate electrode from the gate insulating film in space. This method precisely controls the thermal oxide film formed at the lateral side of the gate electrode, so that the distance between the gate electrode and the electron emission cathode can be accurately adjusted. The electron emission cathodes are homogeneous in shape. Also, the reliability of the display can be improved since a silicide metal is formed on the electron emission cathodes.

Abstract translation: 在一种方法中，通过沟槽的侧壁暴露的用于栅电极的膜被热处理以生长热氧化膜，然后在栅电极的横向侧被去除，以将栅电极与空穴分离 栅极绝缘膜在空间。 该方法精确地控制在栅电极的侧面形成的热氧化膜，从而可以精确地调节栅电极和电子发射阴极之间的距离。 电子发射阴极的形状是均匀的。 此外，由于在电子发射阴极上形成硅化物金属，所以可以提高显示器的可靠性。