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101 条记录 (耗时 0.029 秒)

    Apparatus for improving linearity of small signal
    1.
    发明授权
    Apparatus for improving linearity of small signal 有权
    改善小信号线性度的装置

    公开(公告)号：US6081159A

    公开(公告)日：2000-06-27

    申请号：US164358

    申请日：1998-10-01

    申请人： Chung Hwan Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu ,  Yeong Cheol Hyeon ,  Min Park

    发明人： Chung Hwan Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu ,  Yeong Cheol Hyeon ,  Min Park

    IPC分类号： H04B1/62 ,  H03F1/32 ,  H03F1/26

    CPC分类号： H03F1/342 ,  H03F1/3205

    摘要： An apparatus for improving linearity of small signal according to the present invention comprises a least of one non-linear signal generating means for receiving a first DC bias larger than a threshold voltage and for generating a non-linear signal; feedback means for returning the non-linear signal from said a least of one non-linear signal generating means; and amplifying means for receiving, amplifying and outputting to an output unit, a second DC bias larger than the threshold voltage and a reversed and feedback non-linear signal such that the non-linear signal is cancelled. The linearizers according to the present invention have a higher linearity and a simple constitution, and thereby being used for various terminals.

    摘要翻译： 根据本发明的用于提高小信号线性度的装置包括至少一个非线性信号发生装置，用于接收大于阈值电压的第一DC偏压并用于产生非线性信号; 用于从所述至少一个非线性信号产生装置返回非线性信号的反馈装置; 以及放大装置，用于对输出单元接收，放大和输出大于阈值电压的第二DC偏置和反相和反馈非线性信号，使得非线性信号被消除。 根据本发明的线性化器具有较高的线性度和简单的结构，从而用于各种端子。

    RF active balun circuit for improving small-signal linearity
    2.
    发明授权
    RF active balun circuit for improving small-signal linearity 有权
    RF主动平衡 - 不平衡转换电路，用于改善小信号线性度

    公开(公告)号：US06473595B1

    公开(公告)日：2002-10-29

    申请号：US09437312

    申请日：1999-11-10

    申请人： Chung Hwan Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu ,  Min Park ,  Dae Yong Kim

    发明人： Chung Hwan Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu ,  Min Park ,  Dae Yong Kim

    IPC分类号： H04B110

    CPC分类号： H03F1/223 ,  H03F1/3205 ,  H03F1/3223

    摘要： The RF active balun circuit for improving a small-signal linearity in a power amplifying circuit of a CDMA system is provided under the construction of a signal amplifier driven by exterior individual direct current gate power VGG1, VGG2, for receiving a communication input signal AC-In and performing a cascode amplification at a normal operation point where a feedback third-order distortion signal becomes large; a distortion signal generator driven by exterior direct current gate power VGG3 different from the above power, for generating the communication input signal AC-In as the third-order distortion signal by nonlinearity of an active element to cancel the third-order distortion signal amplified in the signal amplifier; and an insulator provided for an insulation from a exterior driving power VGG3 applied to the distortion signal generator, thereby maintaining the small size, lower power and high efficient terminal characteristics by using a gain based on gate voltage of FET and the nonlinearity characteristic difference, and improving the linearity of an IC operating by a small signal or medium signal.

    摘要翻译： 用于改善CDMA系统的功率放大电路中的小信号线性度的RF有源平衡 - 不平衡转换器被提供在由外部单独的直流栅极功率VGG1，VGG2驱动的信号放大器的构造下，用于接收通信输入信号AC- 在反馈三阶失真信号变大的正常工作点进行并进行共源共栅放大; 由与上述功率不同的外部直流栅极功率VGG3驱动的失真信号发生器，用于通过有源元件的非线性产生作为三阶失真信号的通信输入信号AC-In，以消除放大的三阶失真信号 信号放大器; 以及提供用于与施加到失真信号发生器的外部驱动电力VGG3绝缘的绝缘体，从而通过使用基于FET的栅极电压的增益和非线性特性差来维持小尺寸，较低功率和高效率的端子特性，以及 改善由小信号或中等信号操作的IC的线性度。

    RADAR APPARATUS
    6.
    发明申请
    RADAR APPARATUS 有权
    雷达装置

    公开(公告)号：US20120262330A1

    公开(公告)日：2012-10-18

    申请号：US13445102

    申请日：2012-04-12

    申请人： Pil Jae PARK ,  Cheon Soo Kim ,  Hyun Kyu Yu ,  Min Park ,  Ik Soo EO

    发明人： Pil Jae PARK ,  Cheon Soo Kim ,  Hyun Kyu Yu ,  Min Park ,  Ik Soo EO

    IPC分类号： G01S13/58

    CPC分类号： G01S13/325 ,  G01S7/003 ,  G01S13/584

    摘要： An embodiment of the present invention relates to a radar apparatus, wherein a distance to a target and a velocity of the target are measured by transmitting a digitally modulated transmitting signal using a digital code and receiving and demodulating an echo signal returned due to reflection of the transmitting signal from the target.

    摘要翻译： 本发明的实施例涉及一种雷达装置，其中通过使用数字码发送数字调制的发射信号来测量与目标的距离和目标的速度，并且接收和解调由于反射而返回的回波信号 从目标传输信号。

    Method for fabricating a inductor of low parasitic resistance and capacitance
    7.
    发明授权
    Method for fabricating a inductor of low parasitic resistance and capacitance 有权
    制造低寄生电阻和电容的电感器的方法

    公开(公告)号：US06395637B1

    公开(公告)日：2002-05-28

    申请号：US09168343

    申请日：1998-10-07

    申请人： Min Park ,  Cheon Soo Kim ,  Hyun Kyu Yu

    发明人： Min Park ,  Cheon Soo Kim ,  Hyun Kyu Yu

    IPC分类号： H01L21302

    CPC分类号： H01F41/041 ,  H01F17/0006 ,  H01F27/34 ,  H01F2017/0046 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present invention relates to a method for fabricating an inductor and, more particularly, to a method for fabricating a spiral inductor used in a monolithic microwave integrated circuit on a silicon substrate using semiconductor fabrication processes. The method for fabricating an inductor, comprising the steps of: forming a first dielectric layer on a silicon substrate and forming a first metal wire on the first dielectric layer, wherein the first metal wire is in contact with an active element formed on the silicon substrate; and alternatively forming dielectric layers and metal layers, wherein the metal layers are electrically connected with an upper metal wire and a lower metal wire and wherein the metal layers are patterned using the dielectric layers as etching mask, whereby a metal corrosion is prevented by using the spiral dielectric pattern as the etching mask.

    摘要翻译： 本发明涉及一种用于制造电感器的方法，更具体地说，涉及使用半导体制造工艺制造在硅衬底上的单片微波集成电路中使用的螺旋电感器的方法。 一种制造电感器的方法，包括以下步骤：在硅衬底上形成第一电介质层并在第一电介质层上形成第一金属线，其中第一金属线与形成在硅衬底上的有源元件接触 ; 还可以形成电介质层和金属层，其中金属层与上金属线和下金属线电连接，并且其中使用电介质层作为蚀刻掩模对金属层进行构图，由此通过使用 螺旋介质图案作为蚀刻掩模。

    Method of manufacturing semiconductor device having stacked gate electrode structure
    8.
    发明授权
    Method of manufacturing semiconductor device having stacked gate electrode structure 失效
    制造具有层叠栅电极结构的半导体器件的方法

    公开(公告)号：US5840609A

    公开(公告)日：1998-11-24

    申请号：US951564

    申请日：1997-10-16

    申请人： Yeong Cheol Hyeon ,  Hyun Kyu Yu

    发明人： Yeong Cheol Hyeon ,  Hyun Kyu Yu

    IPC分类号： H01L21/28 ,  H01L21/3105 ,  H01L21/336 ,  H01L29/49 ,  H01L21/26

    CPC分类号： H01L29/6659 ,  H01L21/31051 ,  H01L29/4925 ,  H01L29/66545

    摘要： A method for manufacturing a semiconductor device having a stacked gate electrode structure of self-aligned polysilicon-metal, which is capable of minimizing the variation in structural and electrical characteristics of the gate electrode, while utilizing the manufacturing process of forming a conventional silicone semiconductor memory device, is disclosed. According to the method for manufacturing a semiconductor device of the present invention, the conventional technique generally used in the manufacturing process of forming the silicon semiconductor device can be effectively utilized. Further, an excessive etch loss in the oxide layer can be restrained by using the oxide spacer of the self-aligned oxide layer in forming the metal layer at the gate electrode structure. Furthermore, it has an advantageous effect that the stable electrical characteristics of the resulting device can be obtained by using the polysilicon layer as a basic constituting material of the gate electrode thereof.

    摘要翻译： 一种用于制造具有自对准多晶硅 - 金属堆叠栅电极结构的半导体器件的方法，其能够最小化栅电极的结构和电特性的变化，同时利用形成常规硅氧烷半导体存储器的制造工艺 设备。 根据本发明的半导体器件的制造方法，可以有效地利用通常用于形成硅半导体器件的制造工艺中的常规技术。 此外，通过在栅极电极结构形成金属层时，通过使用自对准氧化物层的氧化物间隔物，可以抑制氧化物层中的过度的蚀刻损失。 此外，通过使用多晶硅层作为其栅电极的基本构成材料，可以获得所得到的器件的稳定电特性。

    Multi-metal coplanar waveguide
    9.
    发明授权
    Multi-metal coplanar waveguide 有权
    多金属共面波导

    公开(公告)号：US07626476B2

    公开(公告)日：2009-12-01

    申请号：US11690219

    申请日：2007-03-23

    申请人： Cheon Soo Kim ,  Myung Shin Kwak ,  Seong Do Kim ,  Mun Yang Park ,  Hyun Kyu Yu ,  Hee Bum Jung

    发明人： Cheon Soo Kim ,  Myung Shin Kwak ,  Seong Do Kim ,  Mun Yang Park ,  Hyun Kyu Yu ,  Hee Bum Jung

    IPC分类号： H01P3/08

    CPC分类号： H01P3/003

    摘要： A coplanar waveguide CPW using multi-layer interconnection CMOS technology is provided. In the CPW including an interlayer insulator disposed on a substrate, metal multilayers disposed on the interlayer insulator, and a ground line-a signal line-a ground line formed of an uppermost metal layer, when a ground line of a lowermost layer is connected to the ground line of the uppermost layer, intermediate metal layers are designed to gradually increase or decrease in width, or to be uneven so as to maximize an area where an ultra-high frequency spreads, thereby minimizing CPW loss and maximizing a slow wave effect. As a result, it is possible to improve performance of an ultra-high frequency circuit and miniaturize the circuit.

    摘要翻译： 提供了一种使用多层互连CMOS技术的共面波导CPW。 在包括设置在基板上的层间绝缘体的CPW中，设置在层间绝缘体上的金属多层和最下层的接地线的接地线 - 信号线 - 由最上层金属层形成的接地线连接到 最上层的地线，中间金属层被设计成逐渐增加或减小宽度或不均匀，以便使超高频率扩展的面积最大化，由此最小化CPW损耗并最大化慢波效应。 结果，可以提高超高频电路的性能并使电路小型化。

    Frequency calibration loop circuit
    10.
    发明授权
    Frequency calibration loop circuit 失效
    频率校准回路电路

    公开(公告)号：US08031009B2

    公开(公告)日：2011-10-04

    申请号：US12581105

    申请日：2009-10-16

    申请人： Byung Hun Min ,  Ja Yol Lee ,  Seong Do Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu

    发明人： Byung Hun Min ,  Ja Yol Lee ,  Seong Do Kim ,  Cheon Soo Kim ,  Hyun Kyu Yu

    IPC分类号： H03L7/085 ,  H03L7/095 ,  H03L7/18 ,  H03L7/081

    CPC分类号： H03L7/181 ,  H03L2207/50 ,  Y10S331/02

    摘要： A frequency calibration loop circuit having a pre-set frequency channel word (FCW) command value, a bit inputted to obtain a target frequency in an oscillator and a pre-set minimum division ratio n (n is a constant) of a programmable divider, includes: an oscillator adjusting an oscillation frequency of an oscillation signal according to a control value; a programmable divider dividing the oscillation signal according to a division ratio to output a divided signal; a counter counting the number of clocks of the divided signal for one cycle of a reference signal to output a count value; and a frequency detector obtaining the control value by subtracting the count value from a reference comparison value, wherein the reference comparison value is obtained by dividing a Frequency Channel Word (FCW) command value by a minimum division ratio of the programmable divider.

    摘要翻译： 一种频率校准环路电路，具有预定的频道字（FCW）指令值，为了获得振荡器中的目标频率输入的比特和可编程分频器的预设最小分频比n（n是常数） 包括：振荡器，根据控制值调整振荡信号的振荡频率; 可编程分频器，根据分频比除以振荡信号，输出分频信号; 计数针对参考信号的一个周期的分频信号的时钟数，以输出计数值; 以及频率检测器，通过从参考比较值中减去计数值来获得控制值，其中通过将频率通道字（FCW）指令值除以可编程分频器的最小分频比来获得参考比较值。