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    THREE-DIMENSIONAL RESISTIVE RANDOM ACCESS MEMORY DEVICES, METHODS OF OPERATING THE SAME, AND METHODS OF FABRICATING THE SAME
    2.
    发明申请
    THREE-DIMENSIONAL RESISTIVE RANDOM ACCESS MEMORY DEVICES, METHODS OF OPERATING THE SAME, AND METHODS OF FABRICATING THE SAME 有权
    三维电阻随机访问存储器件，其操作方法及其制造方法

    公开(公告)号：US20130328005A1

    公开(公告)日：2013-12-12

    申请号：US13783663

    申请日：2013-03-04

    Applicant: Yoocheol Shin ,  Min Kyu Yang

    Inventor： Yoocheol Shin ,  Min Kyu Yang

    IPC: H01L27/24

    CPC classification number: H01L27/2436 ,  H01L27/2454 ,  H01L27/2481 ,  H01L45/08 ,  H01L45/1233 ,  H01L45/146

    Abstract: A semiconductor device includes a substrate extending in a horizontal direction. An active pillar is present on the substrate extending in a vertical direction relative to the horizontal direction of extension of the substrate. A variable resistive pattern is present on the substrate extending in the vertical direction along the active pillar, an electrical resistance of the variable resistive pattern being variable in response to an oxidation or reduction thereof. A gate is present at a sidewall of the active pillar.

    Abstract translation: 半导体器件包括沿水平方向延伸的衬底。 有源柱存在于基板上，相对于基板的延伸水平方向在垂直方向上延伸。 可变电阻图案存在于沿着有源柱沿垂直方向延伸的衬底上，可变电阻图案的电阻响应于氧化或还原而变化。 门处于活动柱的侧壁处。

    Nonvolatile NAND-type memory devices including charge storage layers connected to insulating layers
    5.
    发明授权
    Nonvolatile NAND-type memory devices including charge storage layers connected to insulating layers 失效
    包括连接到绝缘层的电荷存储层的非易失性NAND型存储器件

    公开(公告)号：US08064259B2

    公开(公告)日：2011-11-22

    申请号：US12617972

    申请日：2009-11-13

    Applicant: Changhyun Lee ,  Jungdal Choi ,  Yoocheol Shin ,  Yongsik Yim

    Inventor： Changhyun Lee ,  Jungdal Choi ,  Yoocheol Shin ,  Yongsik Yim

    IPC: G11C11/34

    CPC classification number: G11C16/0466

    Abstract: A nonvolatile memory device includes a word line group including a plurality of middle word lines and an edge word line having charge storage patterns on a substrate. A peripheral line is disposed on one side of the word line group so that the edge word line is between the peripheral word line and the middle word lines. The peripheral line includes an insulating layer and a gate electrode. Charge storage patterns of the middle and edge word lines are separated from each other, and a charge storage pattern of the edge word line extends on one side to be connected to the insulating layer of the peripheral line. Methods of forming nonvolatile memory devices are also disclosed.

    Abstract translation: 非易失性存储器件包括一个包括多个中间字线的字线组和在衬底上具有电荷存储图案的边缘字线。 外围线设置在字线组的一侧，使得边缘字线在周边字线和中间字线之间。 外围线包括绝缘层和栅电极。 中间和边缘字线的电荷存储模式彼此分离，并且边缘字线的电荷存储模式在一侧延伸以连接到外围线的绝缘层。 还公开了形成非易失性存储器件的方法。

    Nonvolatile memory devices that utilize dummy memory cells to improve data reliability in charge trap memory arrays
    9.
    发明授权
    Nonvolatile memory devices that utilize dummy memory cells to improve data reliability in charge trap memory arrays 有权
    利用虚拟存储器单元提高电荷陷阱存储器阵列中的数据可靠性的非易失性存储器件

    公开(公告)号：US07821834B2

    公开(公告)日：2010-10-26

    申请号：US12164533

    申请日：2008-06-30

    Applicant: Jongsun Sel ,  Yoocheol Shin ,  Jaesung Sim

    Inventor： Jongsun Sel ,  Yoocheol Shin ,  Jaesung Sim

    IPC: G11C16/04

    CPC classification number: H01L27/11568 ,  G11C16/3468 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    Abstract: A charge trap flash memory device includes a flash memory array having at least a first page of charge trap memory cells therein electrically coupled to a first word line. The first page of charge trap memory cells includes a plurality of addressable memory cells configured to store data to be retrieved during read operations and a plurality of immediately adjacent non-addressable “dummy” memory cells configured to store dummy data that is not retrievable during the read operations. The plurality of dummy memory cells include at least one auxiliary dummy memory cell that operates as a buffer against lateral hole transfer within a charge trap layer of the array.

    Abstract translation: 电荷陷阱闪存器件包括具有电耦合到第一字线的至少第一页电荷陷阱存储单元的闪存阵列。 电荷陷阱存储器单元的第一页包括多个可寻址存储器单元，其被配置为存储在读取操作期间要检索的数据，以及多个紧邻的不可寻址的“虚拟”存储单元，其被配置为存储在该期间不可检索的伪数据 阅读操作。 多个虚拟存储单元包括至少一个辅助虚拟存储单元，其作为抵抗阵列的电荷陷阱层内的侧向空穴传输的缓冲器而起作用。

    NONVOLATILE MEMORY DEVICES THAT UTILIZE DUMMY MEMORY CELLS TO IMPROVE DATA RELIABILITY IN CHARGE TRAP MEMORY ARRAYS
    10.
    发明申请
    NONVOLATILE MEMORY DEVICES THAT UTILIZE DUMMY MEMORY CELLS TO IMPROVE DATA RELIABILITY IN CHARGE TRAP MEMORY ARRAYS 有权
    非易失性存储器件，利用DUMMY存储器单元来提高电荷捕获存储器阵列中的数据可靠性

    公开(公告)号：US20090168532A1

    公开(公告)日：2009-07-02

    申请号：US12164533

    申请日：2008-06-30

    Applicant: Jongsun Sel ,  Yoocheol Shin ,  Jaesung Sim

    Inventor： Jongsun Sel ,  Yoocheol Shin ,  Jaesung Sim

    IPC: G11C16/06 ,  H01L29/792

    CPC classification number: H01L27/11568 ,  G11C16/3468 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

    Abstract: A charge trap flash memory device includes a flash memory array having at least a first page of charge trap memory cells therein electrically coupled to a first word line. The first page of charge trap memory cells includes a plurality of addressable memory cells configured to store data to be retrieved during read operations and a plurality of immediately adjacent non-addressable “dummy” memory cells configured to store dummy data that is not retrievable during the read operations. The plurality of dummy memory cells include at least one auxiliary dummy memory cell that operates as a buffer against lateral hole transfer within a charge trap layer of the array.

    Abstract translation: 电荷陷阱闪存器件包括具有电耦合到第一字线的至少第一页电荷陷阱存储单元的闪存阵列。 电荷陷阱存储器单元的第一页包括多个可寻址存储器单元，其被配置为存储在读取操作期间要检索的数据，以及多个紧邻的不可寻址的“虚拟”存储单元，其被配置为存储在该期间不可检索的伪数据 阅读操作。 多个虚拟存储单元包括至少一个辅助虚拟存储单元，其作为抵抗阵列的电荷陷阱层内的侧向空穴传输的缓冲器而起作用。

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