公开(公告)号：US09100014B2

公开(公告)日：2015-08-04

申请号：US12919336

申请日：2009-01-08

申请人： Hiromitsu Kimura ,  Takaaki Fuchikami ,  Yoshikazu Fujimori

发明人： Hiromitsu Kimura ,  Takaaki Fuchikami ,  Yoshikazu Fujimori

IPC分类号： G06F12/00 ,  H03K19/20 ,  G11C11/22 ,  H03K3/037

CPC分类号： H03K19/20 ,  G11C11/22 ,  H03K3/0375

摘要： Provided is a nonvolatile storage gate embedded logic circuit embedding a nonvolatile storage gate which can hold data after power supply cutoff and can cut off a power supply at the same time shifting into a standby state. The nonvolatile storage gate embedded logic circuit includes a logic calculation unit having a logic gate, and a nonvolatile storage gate having a nonvolatile storage element, a data interface control unit disposed so as to be adjoining to the nonvolatile storage element, and receiving a nonvolatile storage control signal for data read-out from the nonvolatile storage element and data write-in to the nonvolatile storage element, and a volatile storage element disposed so as to be adjoining to the nonvolatile storage element, receiving a data input signal and a clock signal, and outputting a data output signal.

摘要翻译： 提供了嵌入非易失性存储栅极的非易失性存储栅极嵌入式逻辑电路，其可以在电源切断之后保持数据，并且可以在同时切换到待机状态的同时切断电源。 非易失性存储门嵌入逻辑电路包括具有逻辑门的逻辑计算单元和具有非易失性存储元件的非易失性存储栅极，与非易失性存储元件邻接配置的数据接口控制单元，以及接收非易失性存储器 用于从非易失性存储元件读出的数据的控制信号和非易失性存储元件的数据写入;以及与非易失性存储元件邻接设置的易失性存储元件，接收数据输入信号和时钟信号， 并输出数据输出信号。

公开(公告)号：US20100321975A1

公开(公告)日：2010-12-23

申请号：US12918396

申请日：2009-01-08

申请人： Hiromitsu Kimura ,  Takaaki Fuchikami ,  Yoshikazu Fujimori

发明人： Hiromitsu Kimura ,  Takaaki Fuchikami ,  Yoshikazu Fujimori

IPC分类号： G11C11/22 ,  G11C11/24

CPC分类号： G11C11/22 ,  G11C7/12 ,  G11C11/4094

摘要： By separately setting a capacitor on BL depending on whether the mode is a DRAM mode or an FRAM mode, it is compatible with improvement in a speed by BL capacitor reduction in the DRAM mode and a sufficient BL capacitance in the FRAM mode.A ferroelectric memory device includes: a plurality of bit lines BL disposed in a column direction; a plurality of word lines WL disposed in a row direction; a plurality of plate lines PL and a bit line capacitor control signal BLC; a ferroelectric memory cell (32) disposed at an intersection of the plurality of bit lines BL, the plurality of word lines WL, and the plurality of plate lines PL, and composed of a ferroelectric capacitor CF and a memory cell transistor QM; and a load capacitor adjustment cell (34) disposed at an intersection of the plurality of bit lines BL and the bit line capacitor control signal BLC, and composed of a load capacitor CL and a load capacitor adjustment transistor QL.

摘要翻译： 通过根据模式是DRAM模式还是FRAM模式单独设置BL上的电容器，通过DRAM模式下的BL电容降低和FRAM模式下的足够的BL电容来提高速度。 铁电存储器件包括：沿列方向设置的多个位线BL; 沿行方向布置的多个字线WL; 多个板线PL和位线电容器控制信号BLC; 设置在所述多个位线BL，所述多个字线WL和所述多个板极线PL的交点的铁电存储器单元（32），并且由铁电电容器CF和存储单元晶体管QM构成; 以及设置在多个位线BL和位线电容器控制信号BLC的交点处的负载电容器调整单元（34），由负载电容器CL和负载电容调整用晶体管QL构成。

公开(公告)号：US20100245970A1

公开(公告)日：2010-09-30

申请号：US12743929

申请日：2008-11-20

申请人： Yoshikazu Fujimori ,  Tsuyoshi Fujii

发明人： Yoshikazu Fujimori ,  Tsuyoshi Fujii

IPC分类号： G02F1/03 ,  H01L29/04

CPC分类号： G02F1/05 ,  G02F1/0136 ,  G02F2201/124

摘要： A light control device includes: a single crystal substrate (10); an electro-optic thin film (20) which is provided on the single crystal substrate (10) and has an electro-optic effect; and a plurality of electrodes (30, 40) which are provided along a crystal axis of the electro-optic thin film and apply an electrical field along the crystal axis of the electro-optic thin film (20).

摘要翻译： 光控制装置包括：单晶基板（10）; 设置在单晶基板（10）上并具有电光效应的电光薄膜（20） 以及沿着电光薄膜的晶轴设置并沿着电光薄膜（20）的晶轴施加电场的多个电极（30,40）。

公开(公告)号：US07672034B2

公开(公告)日：2010-03-02

申请号：US11911314

申请日：2006-04-07

申请人： Yoshikazu Fujimori

发明人： Yoshikazu Fujimori

IPC分类号： G02F1/03

CPC分类号： G02F1/03 ,  B82Y20/00 ,  G02F1/017 ,  G02F1/055 ,  G02F1/21 ,  G02F2001/213

摘要： A manufacturing method is provided for a light modulation device that improves utilization efficiency of light. After forming a first reflective layer using a metallic material such as Pt or the like, on a substrate, a light modulating film is formed using an electro-optic material in which refractive index changes in accordance with an applied electrical field. After that, planarization is carried out so that irregularities on an upper surface of the light modulating film are less than or equal to 1/100 of the wavelength of light incident on the light modulation device. A transparent electrode is then formed using ITO, ZnO, or the like, on the light modulating film, and a second reflective layer including a dielectric multilayer is formed.

摘要翻译： 提供了提高光的利用效率的光调制装置的制造方法。 在使用诸如Pt等的金属材料形成第一反射层之后，在基板上，使用其中折射率根据所施加的电场而改变的电光材料形成光调制膜。 之后，进行平坦化，使得光调制膜的上表面上的凹凸小于或等于入射在光调制装置上的光的波长的1/100。 然后在光调制膜上使用ITO，ZnO等形成透明电极，形成包括电介质多层的第二反射层。

公开(公告)号：US07531862B2

公开(公告)日：2009-05-12

申请号：US10988051

申请日：2004-11-12

申请人： Yoshikazu Fujimori

发明人： Yoshikazu Fujimori

IPC分类号： H01L29/94

CPC分类号： H01L28/55 ,  H01L27/0805

摘要： The invention provides a semiconductor device having a ferroelectric substance capacitor small in the occupying area and large in capacitance and a semiconductor device having a ferroelectric substance capacitor reducing influence of noise and being few in malfunctions. The semiconductor device includes a first capacitor formed on a surface of a semiconductor substrate and a second capacitor of a ferroelectric substance capacitance laminated on the first capacitor so as to connect in series.

摘要翻译： 本发明提供了一种半导体器件，其具有占用面积小且电容量大的铁电体电容器，以及具有铁电体电容器的半导体器件，其减小了噪声的影响并且功能较差。 半导体器件包括形成在半导体衬底的表面上的第一电容器和叠层在第一电容器上以串联连接的铁电体电容器的第二电容器。

公开(公告)号：US20080151600A1

公开(公告)日：2008-06-26

申请号：US12034558

申请日：2008-02-20

申请人： Yoshikazu FUJIMORI

发明人： Yoshikazu FUJIMORI

IPC分类号： G11C11/22

CPC分类号： H03K19/185

摘要： To provide a logical operation circuit and a logical operation device which can performs a logical operation using a ferroelectric capacitor. The area ratio between the ferroelectric capacitors CF1 and CF2 are set such that the potential difference Vdef between voltages Va1 and Va0 is as large as possible, and a transistor MP has a threshold voltage Vth which is about ½·(Va0+Va1). Thus, the ON/OFF operation margin of the transistor MP can be significantly large. As a result, a reading process can be performed at a high speed without using an amplifying circuit such as a sense amplifier. Also, the logical operation circuit and the logical operation device can be highly integrated with ease since no sense amplifier is used.

摘要翻译： 提供可以使用铁电电容器执行逻辑运算的逻辑运算电路和逻辑运算装置。 铁电电容器CF1和CF2之间的面积比被设定为使得电压Va 1和Va 0之间的电位差Vdef尽可能大，并且晶体管MP的阈值电压Vth约为1/2（Va 0 + Va 1）。 因此，晶体管MP的导通/截止操作裕度可能会非常大。 结果，可以高速执行读取处理，而不使用诸如读出放大器的放大电路。 此外，逻辑运算电路和逻辑运算器件可以容易地高度集成，因为没有使用读出放大器。

公开(公告)号：US20080045466A1

公开(公告)日：2008-02-21

申请号：US11572251

申请日：2005-07-19

申请人： Kenji Katsuno ,  Yoshikazu Fujimori ,  Masayuki Isaji

发明人： Kenji Katsuno ,  Yoshikazu Fujimori ,  Masayuki Isaji

IPC分类号： A61K31/7004 ,  A61P1/16

CPC分类号： A61K31/7028 ,  A61K31/155 ,  A61K31/4427 ,  A61K31/57 ,  A61K31/7036

摘要： The present invention provides pharmaceutical compositions useful as agents for the inhibition of progression of diseases associated with abnormal accumulation of liver lipids. In particular, the pharmaceutical compositions of the present invention which comprise as an active ingredient a sodium/glucose co-transporter 2 inhibitor are highly suitable as an agent for the inhibition of progression of not only common fatty liver but also non-alcholic fatty liver disease (NAFL), non-alcholic steatohepatitis (NASH), hypernutritive fatty liver, diabetic fatty liver, alcholic fatty liver disease toxic fatty liver or the like.

摘要翻译： 本发明提供了可用作抑制与肝脂异常积累相关的疾病进展的药物的药物组合物。 特别地，作为活性成分含有钠/葡萄糖共转运体2抑制剂的本发明的药物组合物，作为抑制不仅普通脂肪肝而且还可以是非脂肪性脂肪性肝病 （NAFL），非脂肪性脂肪性肝炎（NASH），高营养性脂肪肝，糖尿病性脂肪肝，胆汁脂肪肝病毒性脂肪肝等。

公开(公告)号：US07218142B2

公开(公告)日：2007-05-15

申请号：US11023831

申请日：2004-12-28

申请人： Hiroshi Nozawa ,  Shinzo Koyama ,  Yoshikazu Fujimori

发明人： Hiroshi Nozawa ,  Shinzo Koyama ,  Yoshikazu Fujimori

IPC分类号： H01L25/00 ,  H03K19/177

CPC分类号： H03K17/693 ,  G11C11/22 ,  H01L2924/0002 ,  H03K17/24 ,  H03K19/17712 ,  H01L2924/00

摘要： A switch circuit that is simple in constitution and capable of reliably controlling a switch cell is provided. Since the, gate terminal G1 of a transistor M1 in a switch cell SC is connected only to the terminal 37 of a transistor M2, when the transistor M2 is set to off, the moving path of the charge accumulated at the gate G1 of the transistor M1 is shut off. Consequently, even if the transistor M2 is set to an on state and immediately set back to an off state, the transistor M1 remains for some period of time in an on or off state corresponding to the switching data given through a bit line BL. It is possible to cause the transistor M1 to remain in an on or off state for a specified period of time without disposing a specific circuit for temporary storing the switching data.

摘要翻译： 提供一种构造简单且能够可靠地控制开关电池的开关电路。 由于开关单元SC中的晶体管M 1的栅极端子G 1仅连接到晶体管M 2的端子37，所以当晶体管M 2被设置为截止时，积聚在栅极的电荷的移动路径 关断晶体管M 1的G 1。 因此，即使晶体管M 2被设置为导通状态并立即恢复为截止状态，晶体管M 1在对应于通过位线BL给出的开关数据的导通或截止状态下保持一段时间 。 可以使晶体管M 1在规定时间段内保持导通或截止状态，而不设置用于临时存储开关数据的特定电路。

公开(公告)号：US20060138451A1

公开(公告)日：2006-06-29

申请号：US11346833

申请日：2006-02-03

申请人： Yoshikazu Fujimori ,  Takashi Nakamura

发明人： Yoshikazu Fujimori ,  Takashi Nakamura

IPC分类号： H01L31/111

CPC分类号： G02F1/0551 ,  G02F1/0027 ,  G02F1/055 ,  G02F2202/42

摘要： A structure includes a substrate and a light modulating film formed on top of the substrate. The light modulating film is made of polycrystalline PLZT containing Pb, Zr, Ti, and La as constituent elements. The film has a La concentration in the range of 5 at % to 30 at %. The relative dielectric constant at a frequency of 1 MHz is higher than or equal to 1200.

摘要翻译： 一种结构包括基板和形成在基板顶部的光调制膜。 光调制膜由含有Pb，Zr，Ti和La的多晶PLZT构成。 该膜的La浓度范围为5at％至30at％。 1MHz频率下的相对介电常数高于或等于1200。

公开(公告)号：US07038930B2

公开(公告)日：2006-05-02

申请号：US10844069

申请日：2004-05-12

申请人： Hiroshi Nozawa ,  Hiroaki Kato ,  Yoshikazu Fujimori

发明人： Hiroshi Nozawa ,  Hiroaki Kato ,  Yoshikazu Fujimori

IPC分类号： G11C11/22

CPC分类号： G11C11/22

摘要： To provide a memory device with a function to perform an operation and a method of performing an operation and storage which can save space and cost and which can start, immediately after the power source is recovered, the processing which was being performed at the time of power failure. A memory cell MC can store two independent data sets; DRAM data (volatile data) and FeRAM data (non-volatile data). Thus, the number of memory cells can be reduced to a half. Also, the DRAM data to be used in the next operation of the two data sets which have been read out for the previous operation are temporarily held in a hold circuit 21 of an operation unit OU and then written back into the memory cell MC in a non-volatile manner as new FeRAM data for preparation of the next operation. Thus, even when the power source is shut down by an unexpected trouble, the data necessary for the next operation are not lost.

摘要翻译： 为了提供具有执行操作的功能的存储器件和执行操作和存储的方法，其可以节省空间和成本，并且可以在电源恢复之后立即开始执行正在执行的处理 电源（检测）失败。 存储单元MC可以存储两个独立的数据集; DRAM数据（易失性数据）和FeRAM数据（非易失性数据）。 因此，存储器单元的数量可以减少到一半。 此外，将用于在先前操作中读出的两个数据组的下次操作中使用的DRAM数据被暂时保存在操作单元OU的保持电路21中，然后被写回到存储单元MC中 作为新的FeRAM数据的非易失性方式，用于准备下一个操作。 因此，即使当电源被意外的故障关闭时，下一个操作所需的数据也不会丢失。