公开(公告)号：US20100213532A1

公开(公告)日：2010-08-26

申请号：US12706319

申请日：2010-02-16

Applicant: Yoshiki KAMATA ,  Yuuichi Kamimuta

Inventor： Yoshiki KAMATA ,  Yuuichi Kamimuta

IPC: H01L29/788 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L21/823821 ,  H01L21/28255 ,  H01L21/823828 ,  H01L21/823857 ,  H01L29/517 ,  H01L29/785 ,  H01L29/7881

Abstract: A semiconductor device is provide, which includes a semiconductor region containing Ge as a major component, an insulating film formed on the semiconductor region, and a metallic film formed on the insulating film. At least a portion of the insulating film in contact with the semiconductor region is constituted by an oxide containing at least one rare-earth element MR and at least one Group IV element MIV selected from Ti and Zr.

Abstract translation: 提供一种半导体器件，其包括以Ge为主要成分的半导体区域，形成在半导体区域上的绝缘膜，以及形成在绝缘膜上的金属膜。 与半导体区域接触的绝缘膜的至少一部分由含有至少一种稀土元素MR和至少一种选自Ti和Zr的IV族元素MIV的氧化物构成。

公开(公告)号：US08154082B2

公开(公告)日：2012-04-10

申请号：US12694592

申请日：2010-01-27

Applicant: Yoshihiko Moriyama ,  Yoshiki Kamata ,  Tsutomu Tezuka

Inventor： Yoshihiko Moriyama ,  Yoshiki Kamata ,  Tsutomu Tezuka

IPC: H01L29/786 ,  H01L21/336

CPC classification number: H01L29/045 ,  B82Y10/00 ,  H01L21/823821 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78687

Abstract: A semiconductor device includes an NMISFET region. The NMISFET region includes a Ge nano wire having a triangular cross section along a direction perpendicular to a channel current direction, wherein two of surfaces that define the triangular cross section of the Ge nano wire are (111) planes, and the other surface that define the triangular cross section of the Ge nano wire is a (100) plane; and an Si layer or an Si1-xGex layer (0

Abstract translation: 半导体器件包括NMISFET区域。 NMISFET区域包括沿着垂直于沟道电流方向的方向具有三角形横截面的Ge纳米线，其中限定Ge纳米线的三角形横截面的两个表面是（111）面，而另一个表面限定 Ge纳米线的三角形截面为（100）面; 和Ge纳米线的（100）面上的Si层或Si1-xGex层（0

公开(公告)号：US20060289895A1

公开(公告)日：2006-12-28

申请号：US11472450

申请日：2006-06-22

Applicant: Yoshiki Kamata

Inventor： Yoshiki Kamata

IPC: H01L31/00

CPC classification number: H01L21/823857 ,  H01L21/28158 ,  H01L21/28255 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/40114 ,  H01L29/495 ,  H01L29/517 ,  H01L29/518

Abstract: A semiconductor device includes a channel region, an oxide film, a gate electrode and source/drain regions. The channel region includes Ge. The oxide film is formed on the channel region. The oxide film includes Si and a metallic element M selected from the group consisting of Zr, Hf, La, Ce, Pr, Nd, Pm, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm, Yb and Lu. The gate electrode is formed on the oxide film. The source/drain regions are disposed across the channel region from each other in a longitudinal direction of the channel region.

Abstract translation: 半导体器件包括沟道区，氧化膜，栅电极和源/漏区。 通道区域包括Ge。 氧化膜形成在沟道区上。 该氧化物膜包括Si和选自Zr，Hf，La，Ce，Pr，Nd，Pm，Sm，Eu，Gd，Tb，Dy，Ho，Er，Tm，Yb和Lu中的金属元素M. 栅电极形成在氧化膜上。 源极/漏极区域在沟道区域的纵向方向上彼此跨越沟道区域设置。

公开(公告)号：US06593618B2

公开(公告)日：2003-07-15

申请号：US09994606

申请日：2001-11-28

Applicant: Yoshiki Kamata ,  Akira Nishiyama

Inventor： Yoshiki Kamata ,  Akira Nishiyama

IPC: H01L2976

CPC classification number: H01L29/4983 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823864 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7835

Abstract: In the first aspect of the invention, a semiconductor device can effectively suppress the adverse short channel effect and the possible occurrence of junction leak current and has a low resistance diffusion layer to realize a short propagation delay time as a plurality of side wall films 4, 5 are formed at least in a part of the area between the gate electrode 3 and an elevated region 8 by laying a plurality of films in an appropriate order.

Abstract translation: 在本发明的第一方面中，半导体器件可以有效地抑制不利的短沟道效应和可能发生的结漏电流，并且具有低电阻扩散层，以实现作为多个侧壁膜4的短传播延迟时间， 5通过以适当的顺序铺设多个膜而至少在栅极电极3和升高区域8之间的区域的一部分中形成。

公开(公告)号：US08575652B2

公开(公告)日：2013-11-05

申请号：US12353330

申请日：2009-01-14

Applicant: Yoshiki Kamata

Inventor： Yoshiki Kamata

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/1083 ,  H01L21/26506 ,  H01L21/28255 ,  H01L29/66477

Abstract: An exemplary embodiment provides a semiconductor device, in which a junction leakage current is reduced in MISFET including a source/drain impurity layer formed in a semiconductor region containing Ge, and a semiconductor device manufacturing method. The semiconductor device includes a channel region which is formed in a semiconductor substrate; a gate insulator which is formed on a surface of the channel region; a gate electrode which is formed on the gate insulator; and source/drain impurity layers which are formed on both sides of the channel region. In the semiconductor device, at least part of the source/drain impurity layer is formed in a semiconductor region containing Ge in the semiconductor substrate, and at least an element selected from a group including S, Se, and Te is contained in the semiconductor region which is deeper than a junction depth of the source/drain impurity layer.

Abstract translation: 示例性实施例提供了一种半导体器件，其中包括在包含Ge的半导体区域中形成的源极/漏极杂质层的MISFET中的结漏电流减小，以及半导体器件制造方法。 半导体器件包括形成在半导体衬底中的沟道区; 栅极绝缘体，其形成在沟道区域的表面上; 形成在栅极绝缘体上的栅电极; 以及形成在沟道区两侧的源/漏杂质层。 在半导体器件中，源极/漏极杂质层的至少一部分形成在半导体衬底中含有Ge的半导体区域中，并且至少从包括S，Se和Te的组中选出的元素包含在半导体区域 其比源/漏杂质层的结深深。

公开(公告)号：US20100187503A1

公开(公告)日：2010-07-29

申请号：US12694592

申请日：2010-01-27

Applicant: Yoshihiko MORIYAMA ,  Yoshiki Kamata ,  Tsutomu Tezuka

Inventor： Yoshihiko MORIYAMA ,  Yoshiki Kamata ,  Tsutomu Tezuka

IPC: H01L27/12 ,  H01L21/762 ,  H01L29/775

CPC classification number: H01L29/045 ,  B82Y10/00 ,  H01L21/823821 ,  H01L29/0665 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/068 ,  H01L29/125 ,  H01L29/165 ,  H01L29/42356 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78687

Abstract: A semiconductor device includes an NMISFET region. The NMISFET region includes a Ge nano wire having a triangular cross section along a direction perpendicular to a channel current direction, wherein two of surfaces that define the triangular cross section of the Ge nano wire are (111) planes, and the other surface that define the triangular cross section of the Ge nano wire is a (100) plane; and an Si layer or an Si1-xGex layer (0

Abstract translation: 半导体器件包括NMISFET区域。 NMISFET区域包括沿着垂直于沟道电流方向的方向具有三角形横截面的Ge纳米线，其中限定Ge纳米线的三角形横截面的两个表面是（111）面，而另一个表面限定 Ge纳米线的三角形截面为（100）面; 和Ge纳米线的（100）面上的Si层或Si1-xGex层（0

公开(公告)号：US20080258264A1

公开(公告)日：2008-10-23

申请号：US12137929

申请日：2008-06-12

Applicant: Yoshiki Kamata ,  Akira Nishiyama ,  Tsunehiro Ino ,  Yuuichi Kamimuta ,  Masahiro Koike

Inventor： Yoshiki Kamata ,  Akira Nishiyama ,  Tsunehiro Ino ,  Yuuichi Kamimuta ,  Masahiro Koike

IPC: H01L29/20 ,  H01L21/469

CPC classification number: H01L29/7881 ,  H01L29/40114 ,  H01L29/513

Abstract: Disclosed is a semiconductor device comprising a Ge semiconductor area, and an insulating film area, formed in direct contact with the Ge semiconductor area, containing metal, germanium, and oxygen.

Abstract translation: 公开了一种半导体器件，其包括与包含金属，锗和氧的Ge半导体区域直接接触形成的Ge半导体区域和绝缘膜区域。

公开(公告)号：US20070290263A1

公开(公告)日：2007-12-20

申请号：US11683062

申请日：2007-03-07

Applicant: Yoshiki KAMATA

Inventor： Yoshiki KAMATA

IPC: H01L27/12 ,  H01L21/20 ,  H01L21/84

CPC classification number: H01L21/84 ,  H01L27/12 ,  H01L29/045 ,  H01L29/78681 ,  H01L29/78684

Abstract: It is made possible to obtain epitaxially grown layers with excellent crystallinity. A semiconductor device includes: a semiconductor layer having crystallinity; a first insulating film formed on the semiconductor layer and having a first opening to reach the semiconductor layer; a first epitaxially grown layer formed on the first insulating film so as to embed the first opening; a second insulating film formed on the first epitaxially grown layer and having a second opening to reach the first epitaxially grown layer; and a second epitaxially grown layer formed on the second insulating film so as to embed the second opening.

Abstract translation: 可以获得具有优异结晶度的外延生长层。 半导体器件包括：具有结晶度的半导体层; 形成在半导体层上并具有到达半导体层的第一开口的第一绝缘膜; 形成在所述第一绝缘膜上以嵌入所述第一开口的第一外延生长层; 形成在第一外延生长层上并具有第二开口以到达第一外延生长层的第二绝缘膜; 以及形成在所述第二绝缘膜上以嵌入所述第二开口的第二外延生长层。

公开(公告)号：US20070020956A1

公开(公告)日：2007-01-25

申请号：US11486252

申请日：2006-07-14

Applicant: Yoshiki Kamata ,  Akira Nishiyama

Inventor： Yoshiki Kamata ,  Akira Nishiyama

IPC: H01L21/31

CPC classification number: H01L21/02181 ,  H01L21/02189 ,  H01L21/31637 ,  H01L21/31645 ,  H01L21/764 ,  H01L23/473 ,  H01L2924/0002 ,  H01L2924/00

Abstract: It is made possible to reduce the influence upon adjacent elements. Voids are provided in a Ge substrate. An insulation film containing Ge is provided to cover top faces of the voids.

Abstract translation: 可以减少对相邻元件的影响。 在Ge衬底中提供空隙。 提供含有Ge的绝缘膜以覆盖空隙的顶面。

公开(公告)号：US20090189189A1

公开(公告)日：2009-07-30

申请号：US12353330

申请日：2009-01-14

Applicant: Yoshiki KAMATA

Inventor： Yoshiki KAMATA

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/1083 ,  H01L21/26506 ,  H01L21/28255 ,  H01L29/66477

Abstract: An exemplary embodiment provides a semiconductor device, in which a junction leakage current is reduced in MISFET including a source/drain impurity layer formed in a semiconductor region containing Ge, and a semiconductor device manufacturing method. The semiconductor device includes a channel region which is formed in a semiconductor substrate; a gate insulator which is formed on a surface of the channel region; a gate electrode which is formed on the gate insulator; and source/drain impurity layers which are formed on both sides of the channel region. In the semiconductor device, at least part of the source/drain impurity layer is formed in a semiconductor region containing Ge in the semiconductor substrate, and at least an element selected from a group including S, Se, and Te is contained in the semiconductor region which is deeper than a junction depth of the source/drain impurity layer.

Abstract translation: 示例性实施例提供了一种半导体器件，其中包括在包含Ge的半导体区域中形成的源极/漏极杂质层的MISFET中的结漏电流减小，以及半导体器件制造方法。 半导体器件包括形成在半导体衬底中的沟道区; 栅极绝缘体，其形成在沟道区域的表面上; 形成在栅极绝缘体上的栅电极; 以及形成在沟道区两侧的源/漏杂质层。 在半导体器件中，源极/漏极杂质层的至少一部分形成在半导体衬底中含有Ge的半导体区域中，并且至少从包括S，Se和Te的组中选出的元素包含在半导体区域 其比源/漏杂质层的结深深。