公开(公告)号：US07000846B2

公开(公告)日：2006-02-21

申请号：US10655580

申请日：2003-09-05

Applicant: Norihiko Hakushi ,  Atsushi Ohba ,  Yoshimasa Yoshimura ,  Takeshi Nakayama

Inventor： Norihiko Hakushi ,  Atsushi Ohba ,  Yoshimasa Yoshimura ,  Takeshi Nakayama

IPC: G06K19/06

CPC classification number: G11C7/22 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4096

Abstract: A semiconductor memory device including a flash memory and a RAM incorporating a pseudo-SRAM contained in an MCP, has an internal transfer control signal for controlling internal data transfer between the flash memory and pseudo-SRAM, and an external transfer control signal for controlling data transfer between an external CPU and pseudo-SRAM, as control signals for the pseudo-SRAM. A flash controller in the RAM controls the internal transfer control signal so as to suspend the internal data transfer between the flash memory and pseudo-SRAM when the external CPU requests access to the pseudo-SRAM during the internal data transfer.

Abstract translation: 包括闪速存储器和包含在MCP中的伪SRAM的RAM的半导体存储器件具有用于控制闪速存储器和伪SRAM之间的内部数据传输的内部传送控制信号和用于控制数据的外部传送控制信号 在外部CPU和伪SRAM之间传输，作为伪SRAM的控制信号。 内部闪存控制器控制内部传输控制信号，以便在内部数据传输期间外部CPU请求访问伪SRAM时，暂停闪速存储器和伪SRAM之间的内部数据传输。

公开(公告)号：US5848076A

公开(公告)日：1998-12-08

申请号：US763101

申请日：1996-12-10

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: G06F12/16 ,  G06F11/10 ,  G06K19/07 ,  H03M13/00 ,  G11C29/00

CPC classification number: G06F11/1068 ,  H03M13/00

Abstract: The memory card of the present invention includes an error correction circuit having an error correction code (ECC) computing circuit for computing the error correction codes, in blocks, for the data stored in a main memory, an ECC memory for storing the error correction codes computed by the ECC computing circuit, an ECC control circuit for comparing error correction codes computed for updated data with error correction codes previously computed for corresponding original data stored in the ECC memory, and for producing a signal indicating the result of the comparison, and an error correction controller for finding and correcting errors based on the result of the comparison produced by the ECC control circuit.

Abstract translation: 本发明的存储卡包括纠错电路，该纠错电路具有纠错码（ECC）计算电路，用于以块为单位计算存储在主存储器中的数据的纠错码; ECC存储器，用于存储纠错码 由ECC计算电路计算的ECC控制电路，用于将针对更新数据计算的纠错码与先前为存储在ECC存储器中的相应原始数据计算的纠错码进行比较，并产生指示比较结果的信号的ECC控制电路，以及 纠错控制器，用于根据由ECC控制电路产生的比较结果来查找和校正错误。

公开(公告)号：US5502682A

公开(公告)日：1996-03-26

申请号：US386807

申请日：1995-02-06

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: G06F1/26 ,  G06F12/16 ,  G11C5/14 ,  G11C11/413 ,  G11C13/00

CPC classification number: G11C5/143

Abstract: A semiconductor integrated circuit for controlling a power source with which a power source potential on the basis of different external power source potentials, for example, 5 V and 3 V, can accurately be obtained. The semiconductor integrated circuit for switching between an external power source and a backup power source has an arrangement that, when the external power source potential is supplied to an external power source potential node, the potential at a first connection node on the basis of the external power source potential and a first reference potential of a first reference potential generating circuit are subjected to a comparison by a first comparator, and a first power source potential discriminating portion transmits a first comparison result signal. The potential of a second connection node and a second reference potential of a second reference potential generating circuit are subjected to a comparison by a second comparator, and a second power source potential discriminating portion transmits a second comparison result signal. If the potential of a setting node is high, a switching signal output portion transmits a switching signal corresponding to the first comparison result and transmits a switching signal corresponding to the second comparison result signal if the potential of the setting node is low. If the switching signal indicates a high level, a transistor connected to the external power source potential node is turned on. If the same indicates a low level, a transistor connected to the backup power source is turned on.

Abstract translation: 可以精确地获得用于控制基于不同外部电源电位的电源电位（例如5V和3V）的电源的半导体集成电路。 用于在外部电源和备用电源之间切换的半导体集成电路具有如下设置：当外部电源电位被提供给外部电源电位节点时，基于外部电源电位在第一连接节点处的电位 电源电位和第一参考电位产生电路的第一参考电位由第一比较器进行比较，第一电源电位鉴别部分发送第一比较结果信号。 通过第二比较器对第二参考电位产生电路的第二连接节点和第二参考电位的电位进行比较，第二电源电位鉴别部分发送第二比较结果信号。 如果设置节点的电位高，则切换信号输出部分发送与第一比较结果相对应的切换信号，并且如果设置节点的电位低，则发送与第二比较结果信号相对应的切换信号。 如果开关信号指示高电平，则连接到外部电源电位节点的晶体管导通。 如果相同表示低电平，则连接到备用电源的晶体管被​​接通。

公开(公告)号：US07427031B2

公开(公告)日：2008-09-23

申请号：US11252584

申请日：2005-10-19

Applicant: Norihiko Hakushi ,  Atsushi Ohba ,  Yoshimasa Yoshimura ,  Takeshi Nakayama

Inventor： Norihiko Hakushi ,  Atsushi Ohba ,  Yoshimasa Yoshimura ,  Takeshi Nakayama

IPC: G06K19/06

CPC classification number: G11C7/22 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4096

Abstract: A semiconductor memory device including a flash memory and a RAM incorporating a pseudo-SRAM contained in an MCP, has an internal transfer control signal for controlling internal data transfer between the flash memory and pseudo-SRAM, and an external transfer control signal for controlling data transfer between an external CPU and pseudo-SRAM, as control signals for the pseudo-SRAM. A flash controller in the RAM controls the internal transfer control signal so as to suspend the internal data transfer between the flash memory and pseudo-SRAM when the external CPU requests access to the pseudo-SRAM during the internal data transfer.

Abstract translation: 包括闪速存储器和包含在MCP中的伪SRAM的RAM的半导体存储器件具有用于控制闪速存储器和伪SRAM之间的内部数据传输的内部传送控制信号和用于控制数据的外部传送控制信号 在外部CPU和伪SRAM之间传输，作为伪SRAM的控制信号。 内部闪存控制器控制内部传输控制信号，以便在内部数据传输期间外部CPU请求访问伪SRAM时，暂停闪速存储器和伪SRAM之间的内部数据传输。

公开(公告)号：US5933854A

公开(公告)日：1999-08-03

申请号：US541300

申请日：1995-10-10

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: G06F12/14 ,  G06F3/06 ,  G06F3/08 ,  G06F21/00 ,  G06F21/24 ,  G06K17/00 ,  H04L9/30

CPC classification number: G06F21/78 ,  G06F21/85 ,  G06F2211/008

Abstract: In a system wherein a memory card is connected to a computer, data stored in a memory device in the memory card is read by a processor provided in the computer. An address signal and a data signal from the computer to the memory card, and/or a data signal from the memory card to the computer are coded with coding keys by a coder, while the coded signal is decoded by a decoder with a decoding key corresponding to the coding keys. The coder and the decoder adopts a public key system, and it is difficult to determine the decoding key even if the coding keys are known. In modified examples, coding keys are not provided beforehand in the computer or memory card, and they are latched in a latch device when the memory card is connected to the computer. When the coding keys and decoding keys are stored in the memory card, they are changed for each memory card.

Abstract translation: 在其中存储卡连接到计算机的系统中，存储在存储卡中的存储器件中的数据由计算机中提供的处理器读取。 来自计算机到存储卡的地址信号和数据信号，和/或从存储卡到计算机的数据信号由编码器用编码键编码，而编码信号由译码器用解码密钥解码 对应于编码密钥。 编码器和解码器采用公共密钥系统，即使已知编码密钥，也难以确定解码密钥​​。 在修改示例中，编码密钥不是预先在计算机或存储卡中提供，并且当存储卡连接到计算机时它们被锁存在锁存装置中。 当编码键和解码键存储在存储卡中时，每个存储卡都被更改。

公开(公告)号：US20060065746A1

公开(公告)日：2006-03-30

申请号：US11252584

申请日：2005-10-19

Applicant: Norihiko Hakushi ,  Atsushi Ohba ,  Yoshimasa Yoshimura ,  Takeshi Nakayama

Inventor： Norihiko Hakushi ,  Atsushi Ohba ,  Yoshimasa Yoshimura ,  Takeshi Nakayama

IPC: G06K19/06

CPC classification number: G11C7/22 ,  G11C7/1006 ,  G11C11/406 ,  G11C11/40615 ,  G11C11/4096

Abstract: A semiconductor memory device including a flash memory and a RAM incorporating a pseudo-SRAM contained in an MCP, has an internal transfer control signal for controlling internal data transfer between the flash memory and pseudo-SRAM, and an external transfer control signal for controlling data transfer between an external CPU and pseudo-SRAM, as control signals for the pseudo-SRAM. A flash controller in the RAM controls the internal transfer control signal so as to suspend the internal data transfer between the flash memory and pseudo-SRAM when the external CPU requests access to the pseudo-SRAM during the internal data transfer.

公开(公告)号：US06724678B2

公开(公告)日：2004-04-20

申请号：US10281249

申请日：2002-10-28

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: G11C700

CPC classification number: G11C16/30

Abstract: A nonvolatile semiconductor memory unit which is provided with a nonvolatile semiconductor memory and a controller for performing a read operation, a write operation and an erase operation on the nonvolatile semiconductor memory unit, including an external power source which derives its supply of electric power from outside, an internal power source which derives its supply of electric power from a secondary battery and is connected to the nonvolatile semiconductor memory and the controller, a voltage detecting circuit for detecting a voltage of the external power source and a switching circuit which is provided between the external power source and the internal power source and is subjected to on-off control by an output of the voltage detecting circuit so as to enable and disable the external power source, respectively.

Abstract translation: 一种非易失性半导体存储单元，其具有非易失性半导体存储器和用于对非易失性半导体存储单元执行读取操作，写入操作和擦除操作的控制器，包括从外部获得电力供应的外部电源 内部电源，其从二次电池导出其电力供应并且连接到非易失性半导体存储器和控制器，用于检测外部电源的电压的电压检测电路和设置在所述外部电源之间的开关电路 外部电源和内部电源，并且通过电压检测电路的输出进行开关控制，以分别启用和禁用外部电源。

公开(公告)号：US6126071A

公开(公告)日：2000-10-03

申请号：US195211

申请日：1998-11-18

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: G06F12/14 ,  G06F21/24 ,  G06K17/00 ,  G06K19/07 ,  G06K19/073 ,  G07F7/10 ,  G06K5/00

CPC classification number: G07F7/1008 ,  G06Q20/341 ,  G06Q20/40975

Abstract: An IC memory card and an IC memory card system prevent the use of unauthorized or illegal copies or forgeries of IC memory cards storing original content. Using a key value selected by a terminal device of the IC memory card system, the terminal device calculates a first value and the IC memory card separately calculates a third value by applying a particular method to the key value. Second and fourth values are similarly calculated using a different particular method. The IC memory card then determines whether the first and third values are the same. The terminal device separately determines whether the second and fourth values are the same. Only if the first and third values are confirmed to match, and then the second and fourth values are also confirmed to match, does the terminal device recognize the IC memory card as an authentic IC memory card and not an unauthorized or illegal copy or forgery.

Abstract translation: IC存储卡和IC存储卡系统防止使用存储原始内容的IC存储卡的未授权或非法拷贝或伪造。 使用由IC存储卡系统的终端装置选择的键值，终端装置计算第一值，并且IC存储卡通过将特定方法应用于键值来分别计算第三值。 使用不同的特定方法类似地计算第二和第四值。 然后，IC存储卡确定第一和第三值是否相同。 终端设备分别确定第二和第四值是否相同。 只有当第一和第三个值被确认匹配，然后第二个和第四个值也被确认匹配时，终端设备是否将IC存储卡识别为可靠的IC存储卡，而不是未授权的或非法的拷贝或伪造。

公开(公告)号：US5958079A

公开(公告)日：1999-09-28

申请号：US867887

申请日：1997-06-03

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: G06F12/16 ,  G06F11/10 ,  G06K17/00 ,  G06K19/07 ,  G11C29/00 ,  G06F13/42

CPC classification number: G06F11/1048

Abstract: A memory card includes an error-correction-code (ECC) controller for generating ECCs, an ECC memory for storing ECCs generated by the ECC controller and an address converter for converting between addresses of the ECC memory and those of a main memory for storing data. The ECC controller generates an ECC to be stored in the ECC memory when a control data is input and the address converter fetches a relationship between an address of the ECC memory at which the generated ECC is stored and that of the main memory at which the control data is stored. Upon reading data stored in the main memory, error check and error correction operations are executed for the control data.

Abstract translation: 存储卡包括用于产生ECC的纠错码（ECC）控制器，用于存储由ECC控制器产生的ECC的ECC存储器和用于在ECC存储器的地址与存储数据的主存储器的地址之间进行转换的地址转换器 。 当输入控制数据时，ECC控制器产生要存储在ECC存储器中的ECC，并且地址转换器获取存储所生成的ECC的ECC存储器的地址与控制数据的主存储器的地址之间的关系 数据被存储。 在读取存储在主存储器中的数据时，对控制数据执行错误检查和纠错操作。

公开(公告)号：US5650974A

公开(公告)日：1997-07-22

申请号：US575542

申请日：1995-12-20

Applicant: Yoshimasa Yoshimura

Inventor： Yoshimasa Yoshimura

IPC: G06F12/16 ,  G11C5/14 ,  G11C13/00

CPC classification number: G11C5/143 ,  G11C5/141

Abstract: A semiconductor device includes a first battery BAT 1; a second battery BAT 2; and switches SW1, SW2, SW3, and SW4. Switching block 13 is provided for switching a power source for backing up a memory 3 to retain data. Also a voltage comparator 5 is provided for comparing an external power supply voltage supplied by the power supply VCC of a host apparatus with a reference voltage Vref. In response to the signal from a main battery presence sensor block for sensing the presence of the first battery BAT 1 and the signal from the voltage comparator 5, the memory 3 is backed up to retain data by the external power supply voltage when it is supplied, and further, the second battery BAT 2 is charged by a charging circuit 6 driven by the external power supply voltage. When neither external power supply voltage nor first battery BAT 1 is present, the second battery BAT 2 backs up the memory 3 to retain data. Therefore, power consumption of both main and auxiliary batteries is lessened and memory backup is performed in an assured manner.

Abstract translation: 半导体器件包括第一电池BAT 1; 第二电池BAT2; 开关SW1，SW2，SW3，SW4。 提供切换块13用于切换用于备份存储器3的电源以保留数据。 此外，还提供电压比较器5，用于将由主机设备的电源VCC提供的外部电源电压与参考电压Vref进行比较。 响应于来自主电池存在传感器块的信号，用于感测第一电池BAT 1的存在和来自电压比较器5的信号，存储器3被备份以在提供时由外部电源电压保持数据 此外，第二电池BAT2由由外部电源电压驱动的充电电路6充电。 当外部电源电压和第一电池BAT 1都不存在时，第二电池BAT2备份存储器3以保留数据。 因此，主电池和辅助电池的功耗降低，并且以可靠的方式进行存储器备份。