公开(公告)号：US20130036852A1

公开(公告)日：2013-02-14

申请号：US13565066

申请日：2012-08-02

申请人： Masahito HISADA ,  Yoshinori TAKANO

发明人： Masahito HISADA ,  Yoshinori TAKANO

IPC分类号： G05G1/10

CPC分类号： G05G1/10 ,  Y10T74/20474

摘要： An operation unit includes a case and an operation member molded integrally through injection molding. The operation member includes an outer surface and a slide portion supported by the case. The slide portion is slidable and movable relative to the case. The operation member further includes a knob operated by an operator, a parting line formed continuously from the slide portion to the knob along the outer surface, and a ridge line formed on the outer surface. At least part of the parting line is formed along the ridge line.

摘要翻译： 操作单元包括通过注射成型一体模制的壳体和操作构件。 操作构件包括外表面和由壳体支撑的滑动部分。 滑动部分相对于壳体是可滑动的和可移动的。 操作构件还包括由操作者操作的旋钮，沿着外表面从滑动部分到旋钮连续形成的分型线和形成在外表面上的脊线。 分离线的至少一部分沿着脊线形成。

公开(公告)号：US06807097B2

公开(公告)日：2004-10-19

申请号：US10661571

申请日：2003-09-15

申请人： Yoshinori Takano ,  Tadayuki Taura ,  Toru Tanzawa

发明人： Yoshinori Takano ,  Tadayuki Taura ,  Toru Tanzawa

IPC分类号： G11C1604

CPC分类号： G11C16/3472 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/3436 ,  G11C16/3481 ,  G11C2211/5621 ,  G11C2211/5634

摘要： A non-volatile semiconductor memory device includes: an array of electrically rewritable nonvolatile data storage memory cells each having a transistor structure with a control gate; reference current source circuit configured to generate a first reference current adaptable for use during an ordinary read operation and a second reference current for use during a verify-read operation for data status verification in one of writing and erasing events; a sense amplifier configured to compare read currents of a selected memory cell as selected during the ordinary read operation and the verify-read operation with the first and second reference currents respectively to thereby perform data detection; and a driver configured to give an identical voltage to the control gate of the selected memory cell presently selected during the ordinary read operation and the verify-read operation.

摘要翻译： 非挥发性半导体存储器件包括：每个具有带控制栅极的晶体管结构的电可重写非易失性数据存储单元的阵列; 参考电流源电路，被配置为生成适于在普通读取操作期间使用的第一参考电流和用于在写入和擦除事件之一中的数据状态验证的验证读取操作期间使用的第二参考电流; 读出放大器，被配置为将普通读取操作期间所选择的所选存储单元的读取电流与验证读取操作分别与第一和第二参考电流进行比较，从而执行数据检测; 以及驱动器，被配置为向在普通读取操作和验证读取操作期间当前选择的所选择的存储器单元的控制栅极提供相同的电压。

公开(公告)号：US06552936B2

公开(公告)日：2003-04-22

申请号：US10052303

申请日：2002-01-18

申请人： Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

发明人： Hitoshi Shiga ,  Yoshinori Takano ,  Toru Tanzawa ,  Shigeru Atsumi

IPC分类号： G11C1604

CPC分类号： G11C7/1021 ,  G11C8/10

摘要： There is disclosed a semiconductor integrated circuit device comprising a memory cell array, row decoder, sense amplifier, column gate with two or more stages connected in series, column gate driving circuit, data latch, multiplexer, and address control circuit, and the multiplexer sequentially selects data corresponding to a predetermined address from a plurality of data latched by the data latch. The address control circuit reverses a driving signal for driving at least one stage of the column gate with two or more stages connected in series and selects the columns designated by the next selected plurality of addresses, while the multiplexer sequentially selects the data corresponding to the predetermined address.

公开(公告)号：US5868486A

公开(公告)日：1999-02-09

申请号：US622359

申请日：1996-03-27

申请人： Yoshinori Takano ,  Mamoru Yoshida

发明人： Yoshinori Takano ,  Mamoru Yoshida

IPC分类号： G02B6/00 ,  F21V8/00 ,  G02F1/1335 ,  G02F1/13357

CPC分类号： G02B6/009 ,  G02B6/0031 ,  G02B6/0071

摘要： A lamp holder 11 is made of white synthetic resin by molding such as injection molding. A reflection sheet 12 made of high-reflectance material such as silver or aluminum has a central portion 12a cut out and is affixed to an inner surface 11a of the lamp holder 11. The light reached the inner surface of the lamp holder 11 of light emitted from a lamp 1 is regularly reflected by the reflection sheet 12 and is diffusively reflected by the cutout portion of the reflection sheet 12. A considerable part of the light reflected on the white surface reaches the vicinity of electrode portions 1a of a discharge tube 1 to enter from an incidence end surface of a light guide in the vicinity of electrode portions 1a. Thus, the difference of light-supplying power between the central portion and the end portions (in the vicinity of the electrode portions 1a) of the lamp is compensated. When the reflection sheet made of a resilient material is used, the reflection sheet can be fixed utilizing the resiliency by putting the reflection sheet along the inner curved surface of the lamp holder. Instead of the reflection sheet, metal (silver or aluminum) may be evaporated on the inner surface of the lamp holder.

摘要翻译： 灯座11由注射成型等成型用白色合成树脂制成。 由诸如银或铝的高反射率材料制成的反射片12具有切割出的中心部分12a并固定到灯座11的内表面11a上。光到达灯座11的内表面 来自灯1的光由反射片12规则地反射并被反射片12的切口部扩散反射。在白色表面上反射的大部分光到达放电管1的电极部分1a附近， 从电极部1a附近的导光体的入射端面入射。 因此，补偿灯的中心部分和端部（在电极部分1a附近）之间的供电能力的差异。 当使用由弹性材料制成的反射片时，可以通过将反射片沿着灯座的内部曲面放置来利用弹性来固定反射片。 代替反射片，可以在灯座的内表面上蒸发金属（银或铝）。

公开(公告)号：US08739649B2

公开(公告)日：2014-06-03

申请号：US13565066

申请日：2012-08-02

申请人： Masahito Hisada ,  Yoshinori Takano

发明人： Masahito Hisada ,  Yoshinori Takano

IPC分类号： G05G1/08

CPC分类号： G05G1/10 ,  Y10T74/20474

摘要： An operation unit includes a case and an operation member molded integrally through injection molding. The operation member includes an outer surface and a slide portion supported by the case. The slide portion is slidable and movable relative to the case. The operation member further includes a knob operated by an operator, a parting line formed continuously from the slide portion to the knob along the outer surface, and a ridge line formed on the outer surface. At least part of the parting line is formed along the ridge line.

摘要翻译： 操作单元包括通过注射成型一体模制的壳体和操作构件。 操作构件包括外表面和由壳体支撑的滑动部分。 滑动部分相对于壳体是可滑动的和可移动的。 操作构件还包括由操作者操作的旋钮，沿着外表面从滑动部分到旋钮连续形成的分型线和形成在外表面上的脊线。 分离线的至少一部分沿着脊线形成。

公开(公告)号：US07071771B2

公开(公告)日：2006-07-04

申请号：US10954271

申请日：2004-10-01

申请人： Yoshinori Takano ,  Tadayuki Taura ,  Toru Tanzawa

发明人： Yoshinori Takano ,  Tadayuki Taura ,  Toru Tanzawa

IPC分类号： G05F1/10

CPC分类号： G11C16/3472 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/28 ,  G11C16/3436 ,  G11C16/3481 ,  G11C2211/5634

摘要： A current difference divider circuit with a plurality of current sources is provided. The divider circuit includes a first current source which is operable to generate a first current, a second current source for generation of a second current less in magnitude than the first current, and a third current source for generating a difference current with its magnitude equivalent to a difference between the first and second currents and for generating a third current resulting from the division thereof. The circuit further includes a fourth current source for generating a fourth current obtainable by mirroring of the second current. The third and fourth currents are added together to provide a fifth current, which is then output.

摘要翻译： 提供了具有多个电流源的电流差分电路。 分频器电路包括第一电流源，其可操作以产生第一电流，第二电流源，用于产生比第一电流更小幅度的第二电流;以及第三电流源，用于产生其电流等于 第一和第二电流之间的差异并且用于产生由其分割产生的第三电流。 电路还包括用于产生可通过镜像第二电流而获得的第四电流的第四电流源。 将第三和第四电流加在一起以提供第五电流，然后输出。

公开(公告)号：US06734719B2

公开(公告)日：2004-05-11

申请号：US10238773

申请日：2002-09-11

申请人： Toru Tanzawa ,  Yoshinori Takano

发明人： Toru Tanzawa ,  Yoshinori Takano

IPC分类号： G05F110

CPC分类号： G11C5/147

摘要： A constant voltage generating circuit comprising following elements is shown: a first constant current generation circuit including a first transistor and a second transistor, configured to generate a first voltage and a first current as determined by an operating point to be determined depending on a difference in threshold voltage between the first and second transistors; a second constant current generation circuit configured to generate a second current proportional to said first current; and a voltage generation circuit including a third transistor having its gate and drain connected together, configured to generate a second voltage when letting said second current flow in said third transistor.

摘要翻译： 示出包括以下元件的恒压产生电路：第一恒流产生电路，包括第一晶体管和第二晶体管，其被配置为产生由操作点确定的第一电压和第一电流，以根据第 所述第一和第二晶体管之间的阈值电压;被配置为产生与所述第一电流成比例的第二电流的第二恒定电流产生电路; 以及包括其栅极和漏极连接在一起的第三晶体管的电压产生电路，被配置为当使所述第二电流流过所述第三晶体管时产生第二电压。

公开(公告)号：US06671203B2

公开(公告)日：2003-12-30

申请号：US10233133

申请日：2002-08-30

申请人： Toru Tanzawa ,  Shigeru Atsumi ,  Akira Umezawa ,  Tadayuki Taura ,  Hitoshi Shiga ,  Yoshinori Takano

发明人： Toru Tanzawa ,  Shigeru Atsumi ,  Akira Umezawa ,  Tadayuki Taura ,  Hitoshi Shiga ,  Yoshinori Takano

IPC分类号： G11C1604

CPC分类号： G11C16/0408 ,  G11C16/08 ,  G11C16/26 ,  G11C29/70

摘要： A nonvolatile semiconductor memory includes first and second nonvolatile memory banks, a data-line for read, a data-line for program and verify, a sense amplifier for read, a sense amplifier for program and verify, and a program circuit. The data-lines are arranged in a region between the first and second nonvolatile memory banks, and selectively connected to the bit-lines of the first and second nonvolatile memory banks. The sense amplifier for read is connected to the data-line for read. The sense amplifier for program and verify and the program circuit are connected to the data-line for program and verify.

摘要翻译： 非易失性半导体存储器包括第一和第二非易失性存储器组，用于读取的数据线，用于编程和验证的数据线，用于读取的读出放大器，用于编程和验证的读出放大器以及程序电路。 数据线布置在第一和第二非易失性存储体之间的区域中，并且选择性地连接到第一和第二非易失性存储体的位线。 用于读取的读出放大器连接到数据线进行读取。 用于程序和验证的读出放大器和程序电路连接到数据线进行程序和验证。

公开(公告)号：US06999365B2

公开(公告)日：2006-02-14

申请号：US10896701

申请日：2004-07-22

申请人： Yoshinori Takano ,  Shigeru Atsumi ,  Toru Tanzawa

发明人： Yoshinori Takano ,  Shigeru Atsumi ,  Toru Tanzawa

IPC分类号： G11C7/02

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C16/28

摘要： A semiconductor memory device is provided using a sense amp circuitry capable of lowering a supply voltage. The semiconductor memory device includes an array of memory cells each configured to store data in accordance with the presence/absence or the magnitude of a current; a sense amp configured to compare a voltage caused on a sense line based on data in a memory cell selected from the array of memory cells with a reference voltage applied to a reference sense line to determine the data; and a reference voltage generator configured to generate the reference voltage applied to the reference sense line.

摘要翻译： 使用能够降低电源电压的读出放大器电路来提供半导体存储器件。 半导体存储器件包括存储单元阵列，每个存储器单元被配置为根据电流的存在/不存在或大小来存储数据; 感测放大器，被配置为基于从存储器单元阵列中选择的存储器单元中的数据与施加到参考感测线的参考电压比较在感测线上引起的电压以确定数据; 以及参考电压发生器，被配置为产生施加到参考感测线的参考电压。

公开(公告)号：US06788601B2

公开(公告)日：2004-09-07

申请号：US10305785

申请日：2002-11-26

申请人： Yoshinori Takano ,  Shigeru Atsumi ,  Toru Tanzawa

发明人： Yoshinori Takano ,  Shigeru Atsumi ,  Toru Tanzawa

IPC分类号： G11C702

CPC分类号： G11C7/062 ,  G11C7/067 ,  G11C7/14 ,  G11C16/28

摘要： A semiconductor memory device comprises memory cell array, a sense amp, and a reference voltage generator. The reference voltage generator includes a reference cell unit containing a reference cell to flow a reference current and a first current source load to supply a current to the reference cell; a reference transistor unit containing a reference transistor to flow a current reflecting the reference current and a second current source load to supply a current to the reference transistor; a control amp for negative feedback control of the reference transistor; a current source transistor; and a third current source load connected to a reference sense line.

摘要翻译： 一种半导体存储器件包括存储单元阵列，一个读出放大器，和一个基准电压generator.The参考电压发生器包括含有参考单元中流动的基准电流和第一电流源负载提供电流的基准的基准电池单元 细胞; 含有参考晶体管的参考晶体管单元中流动反射基准电流和供给电流的参考晶体管的第二电流源负载的电流; 用于参考晶体管的负反馈控制的控制放大器; 电流源晶体管; 以及连接到参考感测线的第三电流源负载。