公开(公告)号：US20110234278A1

公开(公告)日：2011-09-29

申请号：US12816045

申请日：2010-06-15

申请人： Young-Suk SEO

发明人： Young-Suk SEO

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： A semiconductor device includes an internal source clock generation unit configured to output first and second internal source clocks, a clock phase correction unit configured to correct a phase difference between the first and second internal source clocks according to a detection result, and to output first and second phase-corrected internal source clocks, a clock delay unit configured to delay the first and second phase-corrected internal source clocks and to generate first and second delay locked loop (DLL) clocks, and a clock output unit configured to mix phases of the first and second DLL clocks to output a DLL clock, and to output a feedback clock to reflect an actual delay condition of an external source clock path in the first or second DLL clock.

摘要翻译： 一种半导体器件，包括：内部源时钟生成单元，被配置为输出第一和第二内部源时钟;时钟相位校正单元，被配置为根据检测结果校正第一和第二内部源时钟之间的相位差，并且首先输出， 第二相位校正的内部源时钟，时钟延迟单元，被配置为延迟第一和第二相位校正的内部源时钟并产生第一和第二延迟锁定环（DLL）时钟;以及时钟输出单元，被配置为混合 用于输出DLL时钟的第一和第二DLL时钟，并且输出反馈时钟以反映第一或第二DLL时钟中外部源时钟路径的实际延迟状态。

公开(公告)号：US20140002150A1

公开(公告)日：2014-01-02

申请号：US13602246

申请日：2012-09-03

申请人： Young Suk SEO ,  Jin Il CHUNG

发明人： Young Suk SEO ,  Jin Il CHUNG

IPC分类号： H03L7/08

CPC分类号： H03L7/095 ,  H03L7/0812

摘要： A phase detection circuit is configured to generate a phase detection signal by comparing a divided clock signal obtained by dividing a first clock signal to a second clock signal during a deactivation period of a control signal, and generate the phase detection signal by comparing the first and second clock signals during an activation period of the control signal.

摘要翻译： 相位检测电路被配置为通过在控制信号的去激活期间比较通过将第一时钟信号与第二时钟信号进行分频而获得的分频时钟信号相比较来生成相位检测信号，并且通过比较第一和第 在控制信号的激活期间的第二时钟信号。

公开(公告)号：US08193844B2

公开(公告)日：2012-06-05

申请号：US12816045

申请日：2010-06-15

申请人： Young-Suk Seo

发明人： Young-Suk Seo

IPC分类号： H03L7/06

CPC分类号： H03L7/0814

摘要： A semiconductor device includes an internal source clock generation unit configured to output first and second internal source clocks, a clock phase correction unit configured to correct a phase difference between the first and second internal source clocks according to a detection result, and to output first and second phase-corrected internal source clocks, a clock delay unit configured to delay the first and second phase-corrected internal source clocks and to generate first and second delay locked loop (DLL) clocks, and a clock output unit configured to mix phases of the first and second DLL clocks to output a DLL clock, and to output a feedback clock to reflect an actual delay condition of an external source clock path in the first or second DLL clock.

摘要翻译： 一种半导体器件，包括：内部源时钟生成单元，被配置为输出第一和第二内部源时钟;时钟相位校正单元，被配置为根据检测结果校正第一和第二内部源时钟之间的相位差，并且首先输出， 第二相位校正的内部源时钟，时钟延迟单元，被配置为延迟第一和第二相位校正的内部源时钟并产生第一和第二延迟锁定环（DLL）时钟;以及时钟输出单元，被配置为混合 用于输出DLL时钟的第一和第二DLL时钟，并且输出反馈时钟以反映第一或第二DLL时钟中外部源时钟路径的实际延迟状态。

公开(公告)号：US08749281B2

公开(公告)日：2014-06-10

申请号：US13602246

申请日：2012-09-03

申请人： Young Suk Seo ,  Jin Il Chung

发明人： Young Suk Seo ,  Jin Il Chung

IPC分类号： H03L7/18 ,  H03L7/093

CPC分类号： H03L7/095 ,  H03L7/0812

摘要： A phase detection circuit is configured to generate a phase detection signal by comparing a divided clock signal obtained by dividing a first clock signal to a second clock signal during a deactivation period of a control signal, and generate the phase detection signal by comparing the first and second clock signals during an activation period of the control signal.

摘要翻译： 相位检测电路被配置为通过在控制信号的去激活期间比较通过将第一时钟信号与第二时钟信号进行分频而获得的分频时钟信号相比较来生成相位检测信号，并且通过比较第一和第 在控制信号的激活期间的第二时钟信号。

公开(公告)号：US20120154001A1

公开(公告)日：2012-06-21

申请号：US13190004

申请日：2011-07-25

申请人： Young Suk SEO

发明人： Young Suk SEO

IPC分类号： H03L7/081 ,  H03H11/16

CPC分类号： H03L7/0818 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/087 ,  H03L7/10

摘要： A synchronization circuit includes a measurement unit configured to measure a difference between an initial delay amount of an input clock signal and an initial delay amount of a feedback clock signal and generate a phase difference detection signal, an initial delay time setting unit configured to generate an initial delay time setting signal in response to the phase difference detection signal, a shift register configured to generate a shift signal in response to the initial delay time setting signal, and a delay chain having an initial delay time set in response to the shift signal.

摘要翻译： 同步电路包括：测量单元，被配置为测量输入时钟信号的初始延迟量与反馈时钟信号的初始延迟量之间的差异，并产生相位差检测信号;初始延迟时间设置单元， 响应于所述相位差检测信号的初始延迟时间设定信号，被配置为响应于所述初始延迟时间设置信号产生移位信号的移位寄存器，以及响应于所述移位信号设置的初始延迟时间的延迟链。

公开(公告)号：US20110001532A1

公开(公告)日：2011-01-06

申请号：US12792283

申请日：2010-06-02

申请人： Young-Suk Seo

发明人： Young-Suk Seo

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A semiconductor device includes a phase division unit, a clock delay unit, a duty cycle correction clock generation unit, and a duty cycle correction voltage generation unit. The phase division unit is configured to divide a phase of a source clock to generate a first division clock. The clock delay unit is configured to delay the first division clock by a delay amount corresponding to a voltage level of a duty cycle correction voltage to output a second division clock. The duty cycle correction clock generation unit is configured to generate a duty cycle correction clock whose logic level changes at respective edges of the first division clock and the second division clock. The duty cycle correction voltage generation unit is configured to generate the duty cycle correction voltage whose voltage level changes depending on a duty cycle of the duty cycle correction clock.

摘要翻译： 半导体器件包括相分离单元，时钟延迟单元，占空比校正时钟生成单元和占空比校正电压生成单元。 相位分割单元被配置为分割源时钟的相位以产生第一分频时钟。 时钟延迟单元被配置为将第一分频时钟延迟与占空比校正电压的电压电平对应的延迟量，以输出第二分频时钟。 占空比校正时钟产生单元被配置为产生其逻辑电平在第一分时钟和第二分频时钟的各个边缘处改变的占空比校正时钟。 占空比校正电压产生单元被配置为产生其电压电平根据占空比校正时钟的占空比而改变的占空比校正电压。

公开(公告)号：US08519759B2

公开(公告)日：2013-08-27

申请号：US13190004

申请日：2011-07-25

申请人： Young Suk Seo

发明人： Young Suk Seo

IPC分类号： H03L7/06

CPC分类号： H03L7/0818 ,  H03L7/0814 ,  H03L7/0816 ,  H03L7/087 ,  H03L7/10

摘要： A synchronization circuit includes a measurement unit configured to measure a difference between an initial delay amount of an input clock signal and an initial delay amount of a feedback clock signal and generate a phase difference detection signal, an initial delay time setting unit configured to generate an initial delay time setting signal in response to the phase difference detection signal, a shift register configured to generate a shift signal in response to the initial delay time setting signal, and a delay chain having an initial delay time set in response to the shift signal.

摘要翻译： 同步电路包括：测量单元，被配置为测量输入时钟信号的初始延迟量与反馈时钟信号的初始延迟量之间的差异，并产生相位差检测信号;初始延迟时间设置单元， 响应于所述相位差检测信号的初始延迟时间设定信号，被配置为响应于所述初始延迟时间设置信号产生移位信号的移位寄存器，以及响应于所述移位信号设置的初始延迟时间的延迟链。

公开(公告)号：US08149036B2

公开(公告)日：2012-04-03

申请号：US12792283

申请日：2010-06-02

申请人： Young-Suk Seo

发明人： Young-Suk Seo

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A semiconductor device includes a phase division unit, a clock delay unit, a duty cycle correction clock generation unit, and a duty cycle correction voltage generation unit. The phase division unit is configured to divide a phase of a source clock to generate a first division clock. The clock delay unit is configured to delay the first division clock by a delay amount corresponding to a voltage level of a duty cycle correction voltage to output a second division clock. The duty cycle correction clock generation unit is configured to generate a duty cycle correction clock whose logic level changes at respective edges of the first division clock and the second division clock. The duty cycle correction voltage generation unit is configured to generate the duty cycle correction voltage whose voltage level changes depending on a duty cycle of the duty cycle correction clock.

摘要翻译： 半导体器件包括相分离单元，时钟延迟单元，占空比校正时钟生成单元和占空比校正电压生成单元。 相位分割单元被配置为分割源时钟的相位以产生第一分频时钟。 时钟延迟单元被配置为将第一分频时钟延迟与占空比校正电压的电压电平对应的延迟量，以输出第二分频时钟。 占空比校正时钟产生单元被配置为产生其逻辑电平在第一分时钟和第二分频时钟的各个边缘处改变的占空比校正时钟。 占空比校正电压产生单元被配置为产生其电压电平根据占空比校正时钟的占空比而改变的占空比校正电压。

公开(公告)号：US07826583B2

公开(公告)日：2010-11-02

申请号：US11819807

申请日：2007-06-29

申请人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Chang-Sik Yoo ,  Jung-June Park ,  Young-Suk Seo

发明人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Chang-Sik Yoo ,  Jung-June Park ,  Young-Suk Seo

IPC分类号： H03D3/24 ,  H04L7/00 ,  H04L25/00 ,  H04L25/40

CPC分类号： H03D13/004

摘要： A clock data recovery apparatus includes a phase looked loop unit, a voltage control delay line, a phase detection unit, a charge pump unit, and a loop filter unit. The phase looked loop unit outputs a plurality of clock signals which are different from each other in phase and of which frequency is lower than that of data. The voltage control delay line outputs recovered clock signals by delaying the clock signals according to input voltage levels. The phase detection unit outputs recovered data in synchronization with the clock signals, respectively and outputs increment and decrement signals which have wider pulse width than the data by comparing the recovered clock signals with the data. The charge pump unit outputs a corresponding current in response to the increment and decrement signals. The loop filter unit determines an amount of delay in the voltage control delay line by outputting the voltage.

摘要翻译： 时钟数据恢复装置包括相位循环单元，电压控制延迟线，相位检测单元，电荷泵单元和环路滤波器单元。 相位循环单元输出相位不同的多个时钟信号，其频率低于数据的时钟信号。 电压控制延迟线通过根据输入电压电平延迟时钟信号来输出恢复的时钟信号。 相位检测单元分别与时钟信号同步地输出恢复的数据，并通过将恢复的时钟信号与数据进行比较，输出比数据宽的脉冲宽度的增减信号。 电荷泵单元响应于增量和减量信号输出相应的电流。 环路滤波器单元通过输出电压来确定电压控制延迟线中的延迟量。

公开(公告)号：US20080101524A1

公开(公告)日：2008-05-01

申请号：US11819807

申请日：2007-06-29

申请人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Chang-Sik Yoo ,  Jung-June Park ,  Young-Suk Seo

发明人： Chun-Seok Jeong ,  Jae-Jin Lee ,  Chang-Sik Yoo ,  Jung-June Park ,  Young-Suk Seo

IPC分类号： H03D3/24

CPC分类号： H03D13/004

摘要： A clock data recovery apparatus includes a phase looked loop unit, a voltage control delay line, a phase detection unit, a charge pump unit, and a loop filter unit. The phase looked loop unit outputs a plurality of clock signals which are different from each other in phase and of which frequency is lower than that of data. The voltage control delay line outputs recovered clock signals by delaying the clock signals according to input voltage levels. The phase detection unit outputs recovered data in synchronization with the clock signals, respectively and outputs increment and decrement signals which have wider pulse width than the data by comparing the recovered clock signals with the data. The charge pump unit outputs a corresponding current in response to the increment and decrement signals. The loop filter unit determines an amount of delay in the voltage control delay line by outputting the voltage.

摘要翻译： 时钟数据恢复装置包括相位循环单元，电压控制延迟线，相位检测单元，电荷泵单元和环路滤波器单元。 相位循环单元输出相位不同的多个时钟信号，其频率低于数据的时钟信号。 电压控制延迟线通过根据输入电压电平延迟时钟信号来输出恢复的时钟信号。 相位检测单元分别与时钟信号同步地输出恢复的数据，并通过将恢复的时钟信号与数据进行比较，输出比数据宽的脉冲宽度的增减信号。 电荷泵单元响应于增量和减量信号输出相应的电流。 环路滤波器单元通过输出电压来确定电压控制延迟线中的延迟量。