公开(公告)号：US20120099389A1

公开(公告)日：2012-04-26

申请号：US13236972

申请日：2011-09-20

申请人： Chul-woo PARK ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

发明人： Chul-woo PARK ,  Young-hyun Jun ,  Joo-sun Choi ,  Hong-sun Hwang

IPC分类号： G11C11/402 ,  G11C29/00 ,  G11C7/00

CPC分类号： G11C29/808 ,  G06F2213/0038 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/40626 ,  G11C2211/4062

摘要： A memory module can include a plurality of dynamic memory devices that each can include a dynamic memory cell array with respective regions therein, where the plurality of dynamic memory devices can be configured to operate the respective regions responsive to a command. A DRAM management unit can be on the module and coupled to the plurality of dynamic memory devices, and can include a memory device operational parameter storage circuit that is configured to store memory device operational parameters for the respective regions to affect operation of the respective regions responsive to the command.

摘要翻译： 存储器模块可以包括多个动态存储器设备，每个动态存储器设备可以包括其中具有其中各自区域的动态存储器单元阵列，其中多个动态存储器设备可被配置为响应于命令操作相应的区域。 DRAM管理单元可以在模块上并且耦合到多个动态存储器设备，并且可以包括存储器设备操作参数存储电路，其被配置为存储用于各个区域的存储器设备操作参数以影响相应区域的操作 命令。

公开(公告)号：US20110246857A1

公开(公告)日：2011-10-06

申请号：US13078364

申请日：2011-04-01

申请人： Seung-Jun Bae ,  Kwang-Il Park ,  Young-Soo Sohn ,  Young-Hyun Jun ,  Joo-Sun Choi ,  Tae-Young Oh

发明人： Seung-Jun Bae ,  Kwang-Il Park ,  Young-Soo Sohn ,  Young-Hyun Jun ,  Joo-Sun Choi ,  Tae-Young Oh

IPC分类号： H03M13/09 ,  H03M13/05 ,  G06F11/10

CPC分类号： G06F11/1004 ,  H03M13/09

摘要： A memory system includes a memory controller and a memory device. The memory device exchanges data through a first channel with the memory controller, exchanges a first cyclic redundancy check (CRC) code associated with the data through a second channel with the memory controller, and receives a command/address packet including a second CRC code associated with a command/address from the memory controller through a third channel.

摘要翻译： 存储器系统包括存储器控制器和存储器件。 存储器件通过第一通道与存储器控制器交换数据，通过与存储器控制器的第二通道交换与数据相关联的第一循环冗余校验（CRC）代码，并且接收包括相关联的第二CRC码的命令/地址分组 具有来自存储器控制器的命令/地址通过第三通道。

公开(公告)号：US08004311B2

公开(公告)日：2011-08-23

申请号：US12714878

申请日：2010-03-01

申请人： Joung Yeal Kim ,  Young Hyun Jun ,  Bai Sun Kong

发明人： Joung Yeal Kim ,  Young Hyun Jun ,  Bai Sun Kong

IPC分类号： H03K19/0175

CPC分类号： H04L25/0278 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  G11C7/22 ,  H03K19/017509

摘要： An input/output circuit includes an I/O node connected to a pull up and pull down circuit having a pull up and pull down transistors. Data is sent and received at through the I/O node. A level shifter provides voltages including a supply voltage and a high voltage higher than the supply voltage. A signal control circuit controls the voltage level applied to the pull up and pull down circuit. During a data input mode, data is received at the I/O node and the pull up transistor is biased at the high voltage to cut off the pull up transistor. During a data output mode, data is output at the I/O node and the pull down transistor pulls down the I/O node to ground when the output data is low, and the pull up transistor is activated when the output data is high.

摘要翻译： 输入/输出电路包括连接到具有上拉和下拉晶体管的上拉和下拉电路的I / O节点。 通过I / O节点发送和接收数据。 电平移位器提供包括电源电压和高于电源电压的高电压的电压。 信号控制电路控制施加到上拉和下拉电路的电压电平。 在数据输入模式期间，在I / O节点处接收数据，并且上拉晶体管被偏置在高电压以截止上拉晶体管。 在数据输出模式下，在I / O节点输出数据，当输出数据为低电平时，下拉晶体管将I / O节点拉低至地，当输出数据为高电平时，上拉晶体管被激活。

公开(公告)号：US07724073B2

公开(公告)日：2010-05-25

申请号：US12287620

申请日：2008-10-10

申请人： Joung-Yeal Kim ,  Young-Hyun Jun ,  Bai-Sun Kong

发明人： Joung-Yeal Kim ,  Young-Hyun Jun ,  Bai-Sun Kong

IPC分类号： G05F3/02

CPC分类号： G11C5/145

摘要： A charge pump circuit includes initialization units, each of which initializes a boost node to an initialization voltage. Boosting units each boost the boost node to a higher voltage than the initialization voltage in response to an input voltage. First and second pump circuits each include a transfer unit for transferring a voltage of the boost node to an output node and sharing the output node. The transfer unit of the first pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the first pump circuit and the voltage of the boost node of the second pump circuit. The transfer unit of the second pump circuit includes two transfer transistors that are switched in response to a voltage of a control node of the second pump circuit and the voltage of the boost node of the first pump circuit.

摘要翻译： 电荷泵电路包括初始化单元，每个初始化单元将升压节点初始化为初始化电压。 升压单元各自将升压节点升压到比初始化电压高的电压以响应于输入电压。 第一和第二泵电路各自包括用于将升压节点的电压传送到输出节点并共享输出节点的传送单元。 第一泵电路的传送单元包括响应于第一泵电路的控制节点的电压和第二泵电路的升压节点的电压而被切换的两个传输晶体管。 第二泵电路的传送单元包括响应于第二泵电路的控制节点的电压和第一泵电路的升压节点的电压而被切换的两个传输晶体管。

公开(公告)号：US20100045491A1

公开(公告)日：2010-02-25

申请号：US12547204

申请日：2009-08-25

申请人： Seung-jun Bae ,  Young-hyun Jun ,  Joo-sun Choi ,  Kwang-il Park ,  Sang-hyup Kwak

发明人： Seung-jun Bae ,  Young-hyun Jun ,  Joo-sun Choi ,  Kwang-il Park ,  Sang-hyup Kwak

IPC分类号： H03M7/00

CPC分类号： H03M5/06 ,  G11C7/1006

摘要： An input/output (IO) interface includes a data encoder which encodes each of a plurality of pieces of parallel data having different timings and generates a plurality of pieces of encoded data, and an alternating current (AC) coupling transmission unit which transmits the plurality of encoded data in an AC coupling method. The data encoder compares first parallel data with second parallel data from among the plurality of pieces of parallel data on a bit-by-bit basis and obtains the number of bits whose logic states have transited between the first parallel data and the second parallel data. When the number of bits whose logic states have transited is greater than or equal to a reference number of bits, the data encoder inverts bit values of the second parallel data to generate the encoded data. When the number of bits whose logic states have transited is less than the reference number of bits, the data encoder maintains the bit values of the second parallel data to generate the encoded data.

摘要翻译： 输入/输出（IO）接口包括数据编码器，其对具有不同定时的多个并行数据中的每一个进行编码并生成多个编码数据;以及交流（AC）耦合传输单元，其传输多个 的交流耦合方法中的编码数据。 数据编码器在逐位的基础上将第一并行数据与多条并行数据中的第二并行数据进行比较，并且获得其逻辑状态已经在第一并行数据和第二并行数据之间转移的位数。 当逻辑状态已经转移的位数大于或等于参考位数时，数据编码器反转第二并行数据的位值，以产生编码数据。 当逻辑状态已经转移的位数小于参考位数时，数据编码器维持第二并行数据的位值以产生编码数据。

公开(公告)号：US07589580B2

公开(公告)日：2009-09-15

申请号：US11797865

申请日：2007-05-08

申请人： Ho-suk Lee ,  Jae-goo Lee ,  Young-hyun Jun

发明人： Ho-suk Lee ,  Jae-goo Lee ,  Young-hyun Jun

IPC分类号： G05F1/10

CPC分类号： G05F3/30

摘要： Provided are a reference current generating method and a current reference circuit. The reference current generating method includes generating a first current using a NMOS transistor and a second current using a PMOS transistor, calculating a current difference between the first and second currents, generating a third current which has a similar current/temperature slope as the second current by multiplying the current difference by a proportional constant, and generating a reference current by subtracting the third current from the second current.

摘要翻译： 提供了参考电流产生方法和电流参考电路。 参考电流产生方法包括使用NMOS晶体管产生第一电流和使用PMOS晶体管产生第二电流，计算第一和第二电流之间的电流差，产生具有与第二电流相似的电流/温度斜率的第三电流 通过将电流差乘以比例常数，并通过从第二电流减去第三电流来产生参考电流。

公开(公告)号：US20080122523A1

公开(公告)日：2008-05-29

申请号：US12025442

申请日：2008-02-04

申请人： Hyoung-Ryol Hwang ,  Young-Hyun Jun

发明人： Hyoung-Ryol Hwang ,  Young-Hyun Jun

IPC分类号： G05F3/02 ,  G05F3/16

CPC分类号： G11C5/14

摘要： A voltage generation circuit and semiconductor memory device including the same are provided. The voltage generation circuit includes: a voltage level detector, which detects a level of a first high voltage to generate a first high voltage level detection signal and detects a level of a second high voltage to generate a second high voltage level detection signal; a control signal generator, which generates at least four pumping control signals in sequence when the first high voltage level detection signal is active, generates a control signal when the first high voltage level detection signal is inactive, and generates a first one of the at least four pumping control signals in response to a level of a power supply voltage; and a voltage generator, which pumps a boost node in response to the at least four pumping control signals to generate the first high voltage and transmits charge from the boost node to a second high voltage generation terminal in response to the control signal to generate the second high voltage.

摘要翻译： 提供了包括该电压产生电路和半导体存储器件的电压产生电路。 电压产生电路包括：电压电平检测器，其检测第一高电平的电平以产生第一高电压电平检测信号，并检测第二高电平的电平以产生第二高电压电平检测信号; 控制信号发生器，当所述第一高电压电平检测信号有效时，依次产生至少四个泵送控制信号，当所述第一高电压电平检测信号无效时产生控制信号，并且产生至少 四个泵送控制信号响应于电源电压的电平; 以及电压发生器，其响应于所述至少四个泵送控制信号泵送升压节点以产生所述第一高电压，并且响应于所述控制信号将电压从所述升压节点传输到第二高电压发生端子，以产生所述第二高电压 高压。

公开(公告)号：US20070273352A1

公开(公告)日：2007-11-29

申请号：US11797865

申请日：2007-05-08

申请人： Ho-suk Lee ,  Jae-goo Lee ,  Young-hyun Jun

发明人： Ho-suk Lee ,  Jae-goo Lee ,  Young-hyun Jun

IPC分类号： G05F3/16

CPC分类号： G05F3/30

摘要： Provided are a reference current generating method and a current reference circuit. The reference current generating method includes generating a first current using a NMOS transistor and a second current using a PMOS transistor, calculating a current difference between the first and second currents, generating a third current which has a similar current/temperature slope as the second current by multiplying the current difference by a proportional constant, and generating a reference current by subtracting the third current from the second current.

摘要翻译： 提供了参考电流产生方法和电流参考电路。 参考电流产生方法包括使用NMOS晶体管产生第一电流和使用PMOS晶体管产生第二电流，计算第一和第二电流之间的电流差，产生具有与第二电流相似的电流/温度斜率的第三电流 通过将电流差乘以比例常数，并通过从第二电流减去第三电流来产生参考电流。

公开(公告)号：US20070160113A1

公开(公告)日：2007-07-12

申请号：US11566658

申请日：2006-12-04

申请人： Chan-Kyung KIM ,  Young-Hyun JUN

发明人： Chan-Kyung KIM ,  Young-Hyun JUN

IPC分类号： G01K7/00

CPC分类号： G01K7/32 ,  G01K7/01 ,  G11C7/04

摘要： Provided are a temperature sensor using a ring oscillator and temperature detection method using the same. One embodiment of the temperature sensor includes a first pulse generator, a second pulse generator, and a counter. The first pulse generator includes a first ring oscillator and generates a first clock signal having a variable period according to a change in temperature. The second pulse generator includes a second ring oscillator and generates a second clock signal having a fixed period. The counter counts a pulse width of the first clock signal as a function of a pulse width of the second clock signal and generates a temperature code.

摘要翻译： 提供了使用环形振荡器的温度传感器和使用其的温度检测方法。 温度传感器的一个实施例包括第一脉冲发生器，第二脉冲发生器和计数器。 第一脉冲发生器包括第一环形振荡器，并根据温度变化产生具有可变周期的第一时钟信号。 第二脉冲发生器包括第二环形振荡器并产生具有固定周期的第二时钟信号。 计数器根据第二时钟信号的脉冲宽度对第一时钟信号的脉冲宽度进行计数，并产生温度代码。

公开(公告)号：US20050105315A1

公开(公告)日：2005-05-19

申请号：US10973806

申请日：2004-10-26

申请人： Ho-Geun Shin ,  Young-Hyun Jun

发明人： Ho-Geun Shin ,  Young-Hyun Jun

IPC分类号： G11C15/00 ,  G11C29/08

CPC分类号： G11C29/08 ,  G11C15/00

摘要： A method of finding errors in a content addressable memory (CAM) and a CAM cell array, the CAM being capable of finding errors in the CAM cell array, is disclosed. The CAM includes the CAM cell array having a plurality of CAM cells and a match line state storing unit. The match line state storing unit is connected to a word line and a match line of the plurality of CAM cells and has a plurality of state cells in which a logic level of stored data is changed according to a logic level of the match line. Errors in the CAM cell array are found by reading data stored in the plurality of state cells. The data stored in the plurality of state cells are matched when there are no errors in the CAM cell array.

摘要翻译： 公开了一种在内容可寻址存储器（CAM）和CAM单元阵列中发现错误的方法，CAM能够在CAM单元阵列中发现错误。 CAM包括具有多个CAM单元的CAM单元阵列和匹配线状态存储单元。 匹配线状态存储单元连接到多个CAM单元的字线和匹配线，并且具有根据匹配线的逻辑电平改变存储数据的逻辑电平的多个状态单元。 通过读取存储在多个状态单元中的数据来发现CAM单元阵列中的错误。 当CAM单元阵列中没有错误时，存储在多个状态单元中的数据是匹配的。