公开(公告)号：US20120020154A1

公开(公告)日：2012-01-26

申请号：US13185755

申请日：2011-07-19

申请人： Yuko NAMIKI ,  Mitsuaki Honma

发明人： Yuko NAMIKI ,  Mitsuaki Honma

IPC分类号： G11C16/10 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes memory cells storing data in a nonvolatile manner, word lines connected to the memory cells and including a first word line and a second word line which is n-th (n is an integer of 1 or more) from the first word line, and a control circuit configured to control a voltage of a word line to write data to a memory cell so that data are written in order from the first word line to the second word line. In a write sequence of the first word line, the control circuit applies a writing voltage to the second word line before writing a memory cell connected to the first word line.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括以非易失性方式存储数据的存储单元，连接到存储单元的字线，并且包括第n字的第一字线和第二字线（n是整数1） 或更多），以及控制电路，被配置为控制字线的电压以将数据写入存储器单元，使得从第一字线到第二字线的顺序写入数据。 在第一字线的写入序列中，控制电路在写入连接到第一字线的存储单元之前，向第二字线施加写入电压。

公开(公告)号：US20110242892A1

公开(公告)日：2011-10-06

申请号：US13161147

申请日：2011-06-15

申请人： Yuko NAMIKI ,  Takuya Futatsuyama ,  Yuui Shimizu

发明人： Yuko NAMIKI ,  Takuya Futatsuyama ,  Yuui Shimizu

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.

摘要翻译： 一种非易失性半导体存储器件，包括：串联多个存储单元的NAND串和设置在两端的第一和第二选择栅晶体管; 耦合到存储器单元的字线; 以及耦合到第一和第二选择栅晶体管的第一和第二选择栅极线，其中数据读取模式由以下偏置条件定义：所选择的字线被施加有读取电压; 在第一选择栅极线侧的第一非选择字线内的与选定字线相邻的一个被施加第一读取通过电压，而其它被施加的低于第一读取通过电压的第二读取通过电压; 并且布置在第二选择栅线侧的第二未选择字线被施加有高于第一读取电压的第三读取通过电压。

公开(公告)号：US20090238003A1

公开(公告)日：2009-09-24

申请号：US12363963

申请日：2009-02-02

申请人： Yuko NAMIKI ,  Takuya Futatsuyama ,  Yuui Shimizu

发明人： Yuko NAMIKI ,  Takuya Futatsuyama ,  Yuui Shimizu

IPC分类号： G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.

摘要翻译： 一种非易失性半导体存储器件，包括：串联多个存储单元的NAND串和设置在两端的第一和第二选择栅晶体管; 耦合到存储器单元的字线; 以及耦合到第一和第二选择栅晶体管的第一和第二选择栅极线，其中数据读取模式由以下偏置条件定义：所选择的字线被施加有读取电压; 在第一选择栅极线侧的第一非选择字线内的与选定字线相邻的一个被施加第一读取通过电压，而其它被施加的低于第一读取通过电压的第二读取通过电压; 并且布置在第二选择栅线侧的第二未选择字线被施加有高于第一读取电压的第三读取通过电压。

公开(公告)号：US08547744B2

公开(公告)日：2013-10-01

申请号：US13185755

申请日：2011-07-19

申请人： Yuko Namiki ,  Mitsuaki Honma

发明人： Yuko Namiki ,  Mitsuaki Honma

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/26 ,  G11C16/3418

摘要： According to one embodiment, a nonvolatile semiconductor memory device includes memory cells storing data in a nonvolatile manner, word lines connected to the memory cells and including a first word line and a second word line which is n-th (n is an integer of 1 or more) from the first word line, and a control circuit configured to control a voltage of a word line to write data to a memory cell so that data are written in order from the first word line to the second word line. In a write sequence of the first word line, the control circuit applies a writing voltage to the second word line before writing a memory cell connected to the first word line.

摘要翻译： 根据一个实施例，非易失性半导体存储器件包括以非易失性方式存储数据的存储单元，连接到存储单元的字线，并且包括第n字的第一字线和第二字线（n是整数1） 或更多），以及控制电路，被配置为控制字线的电压以将数据写入存储器单元，使得从第一字线到第二字线的顺序写入数据。 在第一字线的写入序列中，控制电路在写入连接到第一字线的存储单元之前，向第二字线施加写入电压。

公开(公告)号：US08493788B2

公开(公告)日：2013-07-23

申请号：US13038928

申请日：2011-03-02

申请人： Yuko Namiki ,  Mitsuaki Honma

发明人： Yuko Namiki ,  Mitsuaki Honma

IPC分类号： G11C11/34 ,  G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/04

摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a column decoder, and a control circuit configured to control the memory cell array and the column decoder. The control circuit is configured to load program data from outside, to execute a first data program in a first even-numbered bit line, to execute a second data program in a first odd-numbered bit line, to execute a verify read of the programmed bit lines, to determine whether a value of the verify read is programmed up to a predetermined threshold value, and to change, in a case where the value of the verify read fails to be programmed to the predetermined threshold value, an order of the first and second data programs, to execute the second data program in the first odd-numbered bit line, and then to execute the first data program in the first even-numbered bit line.

摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列，列解码器和被配置为控制存储单元阵列和列解码器的控制电路。 控制电路被配置为从外部加载程序数据，以执行第一偶数位线中的第一数据程序，以执行第一奇数位线中的第二数据程序，以执行编程的校验读 位线，以确定验证读取的值是否被编程到预定阈值，并且在验证读取的值不能被编程到预定阈值的情况下，改变第一 和第二数据程序，以执行第一奇数位线中的第二数据程序，然后执行第一偶数位线中的第一数据程序。

公开(公告)号：US07965555B2

公开(公告)日：2011-06-21

申请号：US12363963

申请日：2009-02-02

申请人： Yuko Namiki ,  Takuya Futatsuyama ,  Yuui Shimizu

发明人： Yuko Namiki ,  Takuya Futatsuyama ,  Yuui Shimizu

IPC分类号： G11C16/00

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.

摘要翻译： 一种非易失性半导体存储器件，包括：串联多个存储单元的NAND串和设置在两端的第一和第二选择栅晶体管; 耦合到存储器单元的字线; 以及耦合到第一和第二选择栅晶体管的第一和第二选择栅极线，其中数据读取模式由以下偏置条件定义：所选择的字线被施加有读取电压; 在第一选择栅极线侧的第一非选择字线内的与选定字线相邻的一个被施加第一读取通过电压，而其它被施加的低于第一读取通过电压的第二读取通过电压; 并且布置在第二选择栅线侧的第二未选择字线被施加有高于第一读取电压的第三读取通过电压。

公开(公告)号：US08374032B2

公开(公告)日：2013-02-12

申请号：US13161147

申请日：2011-06-15

申请人： Yuko Namiki ,  Takuya Futatsuyama ,  Yuui Shimizu

发明人： Yuko Namiki ,  Takuya Futatsuyama ,  Yuui Shimizu

IPC分类号： G11C16/00

CPC分类号： G11C16/0483 ,  G11C16/26 ,  G11C16/3454

摘要： A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.

摘要翻译： 一种非易失性半导体存储器件，包括：串联多个存储单元的NAND串和设置在两端的第一和第二选择栅晶体管; 耦合到存储器单元的字线; 以及耦合到第一和第二选择栅晶体管的第一和第二选择栅极线，其中数据读取模式由以下偏置条件定义：所选择的字线被施加有读取电压; 在第一选择栅极线侧的第一非选择字线内的与选定字线相邻的一个被施加第一读取通过电压，而其它被施加的低于第一读取通过电压的第二读取通过电压; 并且布置在第二选择栅线侧的第二未选择字线被施加有高于第一读取电压的第三读取通过电压。

公开(公告)号：US08194465B2

公开(公告)日：2012-06-05

申请号：US12883520

申请日：2010-09-16

申请人： Yuko Namiki ,  Takuya Futatsuyama

发明人： Yuko Namiki ,  Takuya Futatsuyama

IPC分类号： G11C11/34

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5621

摘要： A non-volatile semiconductor storage device according to one aspect has a memory cell array, a first wiring, a second wiring, and a control circuit. The control circuit is configured to, at the time of the write operation, control the write operation in each of the memory strings such that a memory cell positioned closer to the second wiring is subject to the write operation earlier, and the write operation sequentially proceeds to farther memory cells. On the other hand, the control circuit is also configured to, at the time of the read operation, apply a higher voltage to gates of unselected memory cells as a selected memory cell is located at a region closer to the first wiring.

摘要翻译： 根据一个方面的非易失性半导体存储器件具有存储单元阵列，第一布线，第二布线和控制电路。 控制电路被配置为在写入操作时控制每个存储器串中的写入操作，使得位于更靠近第二布线的存储单元更早地进行写入操作，并且写入操作顺序地进行 到更多的记忆细胞。 另一方面，控制电路还被配置为，在读取操作时，当选择的存储器单元位于更接近第一布线的区域时，向未选择的存储单元的栅极施加更高的电压。

公开(公告)号：US20110216599A1

公开(公告)日：2011-09-08

申请号：US13038928

申请日：2011-03-02

申请人： Yuko NAMIKI ,  Mitsuaki HONMA

发明人： Yuko NAMIKI ,  Mitsuaki HONMA

IPC分类号： G11C16/04

CPC分类号： G11C16/0483 ,  G11C16/04

摘要： According to one embodiment, a semiconductor memory device includes a memory cell array, a column decoder, and a control circuit configured to control the memory cell array and the column decoder. The control circuit is configured to load program data from outside, to execute a first data program in a first even-numbered bit line, to execute a second data program in a first odd-numbered bit line, to execute a verify read of the programmed bit lines, to determine whether a value of the verify read is programmed up to a predetermined threshold value, and to change, in a case where the value of the verify read fails to be programmed to the predetermined threshold value, an order of the first and second data programs, to execute the second data program in the first odd-numbered bit line, and then to execute the first data program in the first even-numbered bit line.

摘要翻译： 根据一个实施例，半导体存储器件包括存储单元阵列，列解码器和被配置为控制存储单元阵列和列解码器的控制电路。 控制电路被配置为从外部加载程序数据，以执行第一偶数位线中的第一数据程序，以执行第一奇数位线中的第二数据程序，以执行编程的校验读 位线，以确定验证读取的值是否被编程到预定阈值，并且在验证读取的值不能被编程到预定阈值的情况下，改变第一 和第二数据程序，以执行第一奇数位线中的第二数据程序，然后执行第一偶数位线中的第一数据程序。

公开(公告)号：US20110069557A1

公开(公告)日：2011-03-24

申请号：US12883520

申请日：2010-09-16

申请人： Yuko NAMIKI ,  Takuya Futatsuyama

发明人： Yuko NAMIKI ,  Takuya Futatsuyama

IPC分类号： G11C16/34 ,  G11C16/12 ,  G11C16/28

CPC分类号： G11C16/0483 ,  G11C11/5628 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3454 ,  G11C2211/5621

摘要： A non-volatile semiconductor storage device according to one aspect has a memory cell array, a first wiring, a second wiring, and a control circuit. The control circuit is configured to, at the time of the write operation, control the write operation in each of the memory strings such that a memory cell positioned closer to the second wiring is subject to the write operation earlier, and the write operation sequentially proceeds to farther memory cells. On the other hand, the control circuit is also configured to, at the time of the read operation, apply a higher voltage to gates of unselected memory cells as a selected memory cell is located at a region closer to the first wiring.

摘要翻译： 根据一个方面的非易失性半导体存储器件具有存储单元阵列，第一布线，第二布线和控制电路。 控制电路被配置为在写入操作时控制每个存储器串中的写入操作，使得位于更靠近第二布线的存储单元更早地进行写入操作，并且写入操作顺序地进行 到更多的记忆细胞。 另一方面，控制电路还被配置为，在读取操作时，当选择的存储器单元位于更接近第一布线的区域时，向未选择的存储单元的栅极施加更高的电压。