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公开(公告)号：US20110242892A1
公开(公告)日：2011-10-06
申请号：US13161147
申请日：2011-06-15
申请人： Yuko NAMIKI , Takuya Futatsuyama , Yuui Shimizu
发明人： Yuko NAMIKI , Takuya Futatsuyama , Yuui Shimizu
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454
摘要： A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.
摘要翻译： 一种非易失性半导体存储器件，包括：串联多个存储单元的NAND串和设置在两端的第一和第二选择栅晶体管; 耦合到存储器单元的字线; 以及耦合到第一和第二选择栅晶体管的第一和第二选择栅极线，其中数据读取模式由以下偏置条件定义：所选择的字线被施加有读取电压; 在第一选择栅极线侧的第一非选择字线内的与选定字线相邻的一个被施加第一读取通过电压，而其它被施加的低于第一读取通过电压的第二读取通过电压; 并且布置在第二选择栅线侧的第二未选择字线被施加有高于第一读取电压的第三读取通过电压。
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公开(公告)号：US20090238003A1
公开(公告)日：2009-09-24
申请号：US12363963
申请日：2009-02-02
申请人： Yuko NAMIKI , Takuya Futatsuyama , Yuui Shimizu
发明人： Yuko NAMIKI , Takuya Futatsuyama , Yuui Shimizu
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454
摘要： A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.
摘要翻译： 一种非易失性半导体存储器件，包括：串联多个存储单元的NAND串和设置在两端的第一和第二选择栅晶体管; 耦合到存储器单元的字线; 以及耦合到第一和第二选择栅晶体管的第一和第二选择栅极线，其中数据读取模式由以下偏置条件定义：所选择的字线被施加有读取电压; 在第一选择栅极线侧的第一非选择字线内的与选定字线相邻的一个被施加第一读取通过电压，而其它被施加的低于第一读取通过电压的第二读取通过电压; 并且布置在第二选择栅线侧的第二未选择字线被施加有高于第一读取电压的第三读取通过电压。
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公开(公告)号：US08374032B2
公开(公告)日：2013-02-12
申请号：US13161147
申请日：2011-06-15
申请人： Yuko Namiki , Takuya Futatsuyama , Yuui Shimizu
发明人： Yuko Namiki , Takuya Futatsuyama , Yuui Shimizu
IPC分类号： G11C16/00
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454
摘要： A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.
摘要翻译： 一种非易失性半导体存储器件，包括：串联多个存储单元的NAND串和设置在两端的第一和第二选择栅晶体管; 耦合到存储器单元的字线; 以及耦合到第一和第二选择栅晶体管的第一和第二选择栅极线，其中数据读取模式由以下偏置条件定义：所选择的字线被施加有读取电压; 在第一选择栅极线侧的第一非选择字线内的与选定字线相邻的一个被施加第一读取通过电压，而其它被施加的低于第一读取通过电压的第二读取通过电压; 并且布置在第二选择栅线侧的第二未选择字线被施加有高于第一读取电压的第三读取通过电压。
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公开(公告)号：US08194465B2
公开(公告)日：2012-06-05
申请号：US12883520
申请日：2010-09-16
申请人： Yuko Namiki , Takuya Futatsuyama
发明人： Yuko Namiki , Takuya Futatsuyama
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/26 , G11C16/3418 , G11C16/3454 , G11C2211/5621
摘要： A non-volatile semiconductor storage device according to one aspect has a memory cell array, a first wiring, a second wiring, and a control circuit. The control circuit is configured to, at the time of the write operation, control the write operation in each of the memory strings such that a memory cell positioned closer to the second wiring is subject to the write operation earlier, and the write operation sequentially proceeds to farther memory cells. On the other hand, the control circuit is also configured to, at the time of the read operation, apply a higher voltage to gates of unselected memory cells as a selected memory cell is located at a region closer to the first wiring.
摘要翻译： 根据一个方面的非易失性半导体存储器件具有存储单元阵列，第一布线，第二布线和控制电路。 控制电路被配置为在写入操作时控制每个存储器串中的写入操作，使得位于更靠近第二布线的存储单元更早地进行写入操作，并且写入操作顺序地进行 到更多的记忆细胞。 另一方面，控制电路还被配置为，在读取操作时，当选择的存储器单元位于更接近第一布线的区域时，向未选择的存储单元的栅极施加更高的电压。
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公开(公告)号：US20110069557A1
公开(公告)日：2011-03-24
申请号：US12883520
申请日：2010-09-16
申请人： Yuko NAMIKI , Takuya Futatsuyama
发明人： Yuko NAMIKI , Takuya Futatsuyama
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/26 , G11C16/3418 , G11C16/3454 , G11C2211/5621
摘要： A non-volatile semiconductor storage device according to one aspect has a memory cell array, a first wiring, a second wiring, and a control circuit. The control circuit is configured to, at the time of the write operation, control the write operation in each of the memory strings such that a memory cell positioned closer to the second wiring is subject to the write operation earlier, and the write operation sequentially proceeds to farther memory cells. On the other hand, the control circuit is also configured to, at the time of the read operation, apply a higher voltage to gates of unselected memory cells as a selected memory cell is located at a region closer to the first wiring.
摘要翻译： 根据一个方面的非易失性半导体存储器件具有存储单元阵列，第一布线，第二布线和控制电路。 控制电路被配置为在写入操作时控制每个存储器串中的写入操作，使得位于更靠近第二布线的存储单元更早地进行写入操作，并且写入操作顺序地进行 到更多的记忆细胞。 另一方面，控制电路还被配置为，在读取操作时，当选择的存储器单元位于更接近第一布线的区域时，向未选择的存储单元的栅极施加更高的电压。
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公开(公告)号：US07965555B2
公开(公告)日：2011-06-21
申请号：US12363963
申请日：2009-02-02
申请人： Yuko Namiki , Takuya Futatsuyama , Yuui Shimizu
发明人： Yuko Namiki , Takuya Futatsuyama , Yuui Shimizu
IPC分类号： G11C16/00
CPC分类号： G11C16/0483 , G11C16/26 , G11C16/3454
摘要： A non-volatile semiconductor memory device including: a NAND string having multiple memory cells connected in series and first and second select gate transistors disposed on the both ends; word lines coupled to the memory cells; and first and second select gate lines coupled to the first and second select gate transistors, wherein a data read mode is defined by the following bias condition: a selected word line is applied with a read voltage; one adjacent to the selected word line within first unselected word lines disposed on the first select gate line side is applied with a first read pass voltage while the others are applied with a second read pass voltage lower than the first read pass voltage; and second unselected word lines disposed on the second select gate line side are applied with a third read pass voltage higher than the first read voltage.
摘要翻译： 一种非易失性半导体存储器件，包括：串联多个存储单元的NAND串和设置在两端的第一和第二选择栅晶体管; 耦合到存储器单元的字线; 以及耦合到第一和第二选择栅晶体管的第一和第二选择栅极线，其中数据读取模式由以下偏置条件定义：所选择的字线被施加有读取电压; 在第一选择栅极线侧的第一非选择字线内的与选定字线相邻的一个被施加第一读取通过电压，而其它被施加的低于第一读取通过电压的第二读取通过电压; 并且布置在第二选择栅线侧的第二未选择字线被施加有高于第一读取电压的第三读取通过电压。
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公开(公告)号：US08605503B2
公开(公告)日：2013-12-10
申请号：US13711894
申请日：2012-12-12
申请人： Takuya Futatsuyama
发明人： Takuya Futatsuyama
CPC分类号： G06F3/061 , G06F3/0619 , G06F3/0652 , G06F3/0656 , G06F3/0679 , G06F3/0688 , G11C11/5628 , G11C16/0408 , G11C16/045 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C2211/5648
摘要： A nonvolatile semiconductor memory device comprises a cell unit including a first and a second selection gate transistor and a memory string provided between the first and second selection gate transistors and composed of a plurality of serially connected electrically erasable programmable memory cells operative to store effective data; and a data write circuit operative to write data into the memory cell, wherein the number of program stages for at least one of memory cells on both ends of the memory string is lower than the number of program stages for other memory cells, and the data write circuit executes the first stage program to the memory cell having the number of program stages lower than the number of program stages for the other memory cells after the first stage program to the other memory cells.
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公开(公告)号：US08565020B2
公开(公告)日：2013-10-22
申请号：US13053796
申请日：2011-03-22
IPC分类号： G11C16/04
CPC分类号： G11C11/5628 , G11C16/0483 , G11C16/3436
摘要： A memory includes word lines, bit lines, memory cells each having a gate connected to one of the word lines, a word line driver configured to drive voltages of the word lines, and a sense amplifier configured to detect data of the memory cells via the bit lines. The memory cells are connected in series between the bit lines and a source to constitute cell string. The word line driver increases a verification voltage of any of non-selected word lines connected to non-selected memory cells in the cell string at a time of a verify operation in a certain writing loop of a writing stage. The writing stage includes a plurality of writing loops. The writing loops respectively includes a write operation to write data in a selected memory cell in the cell string and a verify operation to verify that the data are written in the selected memory cell.
摘要翻译： 存储器包括字线，位线，各自具有连接到字线之一的栅极的存储单元，配置为驱动字线的电压的字线驱动器，以及经配置以经由该行线检测存储器单元的数据的读出放大器 位线。 存储单元串联在位线和源之间以构成单元串。 在写入阶段的某个写入循环中，在验证操作时，字线驱动器增加连接到单元串中未选择的存储单元的任何未选择字线的验证电压。 写入阶段包括多个写入循环。 写入循环分别包括写入操作以在单元串中的选定的存储单元中写入数据，以及验证操作以验证数据被写入所选存储单元。
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公开(公告)号：US08203885B2
公开(公告)日：2012-06-19
申请号：US13178718
申请日：2011-07-08
申请人： Naofumi Abiko , Takuya Futatsuyama
发明人： Naofumi Abiko , Takuya Futatsuyama
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/5628 , G11C16/10 , G11C16/3454 , G11C2211/5621 , G11C2211/5634 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： According to an embodiment, a nonvolatile semiconductor memory system includes: a nonvolatile semiconductor memory; and a memory controller having: a memory interface unit that inputs commands to the nonvolatile semiconductor memory and inputs or outputs data between the nonvolatile semiconductor memory; a memory that stores writing information indicating a memory cell transistor that is written the latest in each of the NAND cell units; and a processor that sets a read voltage based on the writing information to read out data from the memory cell transistors connected to a first word line; wherein a row controller is configured to set a plurality of levels of the read voltage to be applied to the first word line, with respect to one threshold for discriminating data stored in a memory cell transistors.
摘要翻译： 根据实施例，非易失性半导体存储器系统包括：非易失性半导体存储器; 以及存储器控制器，具有：存储器接口单元，其向非易失性半导体存储器输入命令并在非易失性半导体存储器之间输入或输出数据; 存储器，其存储表示在每个NAND单元单元中写入最新的存储单元晶体管的写入信息; 以及处理器，其基于写入信息设置读取电压，以从连接到第一字线的存储单元晶体管读出数据; 其中行控制器被配置为相对于用于识别存储在存储单元晶体管中的数据的一个阈值来设置要施加到第一字线的读取电压的多个电平。
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公开(公告)号：US20110216593A1
公开(公告)日：2011-09-08
申请号：US13108641
申请日：2011-05-16
IPC分类号： G11C16/04
CPC分类号： G11C16/08 , G11C8/08 , G11C16/0483
摘要： A method of controlling a programming of a flash memory with memory blocks. The method includes checking whether a selected block among the memory blocks belongs to a first group or a second group. The method further includes executing the programming from a least bit address when the selected block belongs to the first group. The method also includes executing the programming from a most bit address when the selected block belongs to the second group.
摘要翻译： 一种利用存储块控制闪速存储器编程的方法。 该方法包括检查存储器块中的所选块是否属于第一组或第二组。 该方法还包括当所选择的块属于第一组时从最小位地址执行编程。 该方法还包括当所选择的块属于第二组时从大多数位地址执行编程。
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