公开(公告)号：US4451897A

公开(公告)日：1984-05-29

申请号：US274808

申请日：1981-06-18

申请人： Yutaka Murao

发明人： Yutaka Murao

IPC分类号： F02D41/34 ,  F02D21/08 ,  F02D37/02 ,  F02D41/26 ,  F02D45/00 ,  F02P5/15 ,  G05B15/02 ,  G05B19/02 ,  G05B19/042 ,  G06F3/00 ,  G06F13/00 ,  G06F15/20

CPC分类号： G05B19/0423 ,  F02D37/02 ,  F02D41/263 ,  F02D41/0077 ,  G05B2219/25403 ,  Y02P90/265

摘要： An output control device for an internal combustion engine has a plurality of registers connected to a data bus. These registers comprise registers for holding output request time data specifying when the generation of output signals will be requested, and mask data specifying whether the registers are reserved for output operations or may be used as working RAM. Other registers are provided for holding output request time data, mask data, and channel designating data specifying the output channel on which output signals will be generated. Unloading of the data in these registers is performed by sequentially supplying gate switching control signals from a shifter to gates connected to these registers. The output request time data is compared with absolute time data from a timer by a comparator, and a coincidence signal indicating coincidence detection is applied to a mask gate together with the mask data. Whether to accept the coincidence data or not is determined according to the value of the mask data. Selectors are also included for determining whether to use the coincidence signal to request an output control signal at a predetermined output channel or at an output channel designated by the channel designating data. The output request data selected through these selectors is supplied to the corresponding output port through flip-flops.

摘要翻译： 用于内燃机的输出控制装置具有连接到数据总线的多个寄存器。 这些寄存器包括用于保持输出请求时间数据的寄存器，用于指定何时将请求产生输出信号，以及掩蔽数据，指定寄存器是否被保留用于输出操作，或者可以用作工作RAM。 提供其他寄存器用于保持输出请求时间数据，掩码数据和指定将在其上生成输出信号的输出通道的通道指定数据。 通过从移位器向连接到这些寄存器的门顺序提供栅极切换控制信号来执行这些寄存器中的数据的卸载。 通过比较器将输出请求时间数据与来自定时器的绝对时间数据进行比较，并且将指示一致检测的一致信号与掩码数据一起施加到掩码门。 根据掩码数据的值确定是否接受符合数据。 还包括选择器，用于确定是否使用一致信号来请求在预定输出通道或由通道指定数据指定的输出通道的输出控制信号。 通过这些选择器选择的输出请求数据通过触发器提供给相应的输出端口。

公开(公告)号：US4459657A

公开(公告)日：1984-07-10

申请号：US304711

申请日：1981-09-22

申请人： Yutaka Murao

发明人： Yutaka Murao

IPC分类号： G06F9/42 ,  G06F9/40 ,  G06F9/46 ,  G06F9/18 ,  G06F13/00

CPC分类号： G06F9/4425 ,  G06F9/461

摘要： A data processing system is disclosed which includes a memory having a plurality of addressable register banks and for memory areas for performing a re-entrant function of a subroutine. The memory areas store a start address of an interrupt program, a program status word of the interrupt program, and a register bank pointer code to be used by the interrupt program. The memory has a program counter, a program status word, and a register bank pointer. When an interrupt request is received, the contents of a program counter, the program status word, and the register bank pointer are swapped with the contents of a particular memory area group. Further, by swapping the contents of the program counter with the contents of the register in the register bank which contains in advance the start address of the subroutine to be used, the re-entrant operation of the subroutine may be accomplished.

摘要翻译： 公开了一种数据处理系统，其包括具有多个可寻址寄存器组的存储器和用于执行子程序的重入功能的存储器区域。 存储区域存储中断程序的起始地址，中断程序的程序状态字和中断程序要使用的寄存器组指针代码。 存储器具有程序计数器，程序状态字和寄存器组指针。 当接收到中断请求时，程序计数器，程序状态字和寄存器组指针的内容与特定存储器区域组的内容进行交换。 此外，通过将寄存器组中的寄存器的内容与预先包含的子例程的开始地址进行交换，可以实现子程序的重入操作。

公开(公告)号：US4352157A

公开(公告)日：1982-09-28

申请号：US118316

申请日：1980-02-04

申请人： Keiji Namimoto ,  Seiji Eguchi ,  Yutaka Murao

发明人： Keiji Namimoto ,  Seiji Eguchi ,  Yutaka Murao

IPC分类号： G06F9/46 ,  G06F9/18 ,  G06F13/00

CPC分类号： G06F9/462

摘要： The data-processing apparatus of this invention comprises a central processing unit (hereinafter referred to as the "CPU"), and a plurality of a groups of memory units in the CPU to be applied as a general register set. The groups of memory units are provided in a number which is equal to the number of interrupt programs and each group has been previously supplied with information on the individual interrupt programs (such information includes, for example, data on entry address, program status word, etc.). The present data-processing apparatus further has a general register-set pointer provided in the CPU. Where the general register set pointer is supplied with a particular numerical value, the corresponding one of the memory unit groups is selectively used as a general register set.

摘要翻译： 本发明的数据处理装置包括中央处理单元（以下称为“CPU”），以及要作为通用寄存器组应用的CPU中的多组存储单元。 存储单元组以等于中断程序的数量的数量提供，并且每个组先前已经提供有关各个中断程序的信息（这样的信息例如包括关于入口地址的数据，程序状态字， 等等。）。 本数据处理装置还具有设置在CPU中的通用寄存器集指针。 在通用寄存器设置指针被提供有特定数值的情况下，存储单元组中对应的一个选择性地用作通用寄存器组。

公开(公告)号：US5335331A

公开(公告)日：1994-08-02

申请号：US728681

申请日：1991-07-12

申请人： Yutaka Murao ,  Tetsuro Wada

发明人： Yutaka Murao ,  Tetsuro Wada

IPC分类号： G06F9/30 ,  G06F9/26 ,  G06F9/318 ,  G06F9/32 ,  G06F9/38 ,  G06F15/78 ,  G06F9/46

CPC分类号： G06F9/32 ,  G06F9/30181 ,  G06F9/30185 ,  G06F9/30189 ,  G06F9/30196 ,  G06F9/382 ,  G06F9/3822

摘要： To increase the kinds of executable instructions of a microcomputer without increasing the number of bits (e.g. 8 bits) constituting one word or instruction, that is, without decreasing the execution speed or increasing the ROM usage, two or more instruction groups including instructions of different kinds, respectively, are provided operation modes are determined for the respective instruction groups; and the respective instruction groups to be executed are switched according to the respective operation modes. The microcomputer includes an instruction register, an execution control unit, a mode memory flip-flop, gates, two predecoders, a programmable logic array, an arithmetic logic unit, etc. The ordinary and special instruction groups can be selected in response to an interrupt entry signal and an interrupt return signal and a specific bit of an instruction, for instance.

摘要翻译： 为了增加微计算机的可执行指令的种类，而不增加构成一个字或指令的位数（例如8位），即，不降低执行速度或增加ROM使用，则两个或多个指令组包括不同的指令 分别为各个指令组确定操作模式; 并且根据各个操作模式切换要执行的各个指令组。 微型计算机包括指令寄存器，执行控制单元，模式存储器触发器，门，两个预解码器，可编程逻辑阵列，算术逻辑单元等。可以响应于中断来选择普通和特殊指令组 例如，输入信号和中断返回信号以及指令的特定位。

公开(公告)号：US4521763A

公开(公告)日：1985-06-04

申请号：US419571

申请日：1982-09-17

申请人： Yutaka Murao ,  Taira Nishizono

发明人： Yutaka Murao ,  Taira Nishizono

IPC分类号： H03M1/60 ,  H03M1/00 ,  H03K13/02

CPC分类号： H03M1/10 ,  H03M1/1205 ,  H03M1/56

摘要： An A-D converter for converting into a pulse train signal an analog input voltage signal from a signal source, said A-D converter comprising a signal generator for providing a low analog input voltage signal of a low fixed level V.sub.L, a signal generator for providing a high analog input voltage signal of a high fixed level V.sub.H, a multiplexer connected to the signal source and the signal generators for receiving the signals therefrom and supplying the signals selectively and successively, a V-T converter connected to the multiplexer for converting a selected one of the analog input voltage signals into a pulse train signal; a memory for storing instruction programs used for A-D conversion, a central processing unit, a first counter connected to the V-T converter for counting pulses of the pulse train signal, said first counter being loaded with a specific value supplied from the central processing unit, a clock pulse generator for producing clock pulse, a second counter connected to the clock pulse generator for counting the clock pulses while the first counter is counting the same and a control circuit.

摘要翻译： 用于转换成脉冲序列的AD转换器从信号源发送模拟输入电压信号，所述AD转换器包括用于提供低固定电平VL的低模拟输入电压信号的信号发生器，用于提供高模拟 高固定电平VH的输入电压信号，连接到信号源的多路复用器和用于从其接收信号的信号发生器，并且选择性地和连续地提供信号;连接到多路复用器的VT转换器，用于将所选择的一个模拟输入 电压信号转成脉冲串信号; 用于存储用于AD转换的指令程序的存储器，中央处理单元，连接到VT转换器的第一计数器，用于计数脉冲串信号的脉冲，所述第一计数器加载从中央处理单元提供的特定值， 用于产生时钟脉冲的时钟脉冲发生器，连接到时钟脉冲发生器的第二计数器，用于在第一计数器计数时对时钟脉冲进行计数和控制电路。

公开(公告)号：US4217638A

公开(公告)日：1980-08-12

申请号：US907856

申请日：1978-05-19

申请人： Keiji Namimoto ,  Seiji Eguchi ,  Yutaka Murao

发明人： Keiji Namimoto ,  Seiji Eguchi ,  Yutaka Murao

IPC分类号： G06F9/46 ,  G06F9/18 ,  G06F13/00

CPC分类号： G06F9/462

摘要： The data-processing apparatus of this invention comprises a central processing unit (hereinafter referred to as the "CPU"), and a plurality of groups of memory units in the CPU to be applied as a general register set. The groups of memory units are provided in a number which is equal to the number of interrupt programs and each group has been previously supplied with information on the individual interrupt programs (such information includes, for example, data on entry address, program status word, etc.). The present data-processing apparatus further has a general register-set pointer provided in the CPU. Where the general register set pointer is supplied with a particular numerical value, the corresponding one of the memory unit groups is selectively used as a general register set.

摘要翻译： 本发明的数据处理装置包括中央处理单元（以下称为“CPU”），以及要作为通用寄存器组应用的CPU中的多组存储单元。 存储单元组以等于中断程序的数量的数量提供，并且每个组先前已经提供有关各个中断程序的信息（这样的信息例如包括关于入口地址的数据，程序状态字， 等等。）。 本数据处理装置还具有设置在CPU中的通用寄存器集指针。 在通用寄存器设置指针被提供有特定数值的情况下，存储单元组中对应的一个选择性地用作通用寄存器组。

公开(公告)号：US4628448A

公开(公告)日：1986-12-09

申请号：US675270

申请日：1984-11-29

申请人： Yutaka Murao

发明人： Yutaka Murao

IPC分类号： G06F13/10 ,  G06F1/22 ,  G06F15/78 ,  G06F9/00

CPC分类号： G06F15/786 ,  G06F1/22 ,  G06F15/7832

摘要： On a single chip microprocessor which has 2.sup.n operation modes, apparatus which permits selecting one mode out of the 2.sup.n operation modes by using only one external pin connection and user program execution. A mode-setting register on the single chip microprocessor can be updated both through the external pin designating one of the two start modes, which are part of the 2.sup.n operation modes, during the reset state of the microprocessor and through a write operation generated by executing a user program during the normal (nonreset) state of the microprocessor.

摘要翻译： 在具有2n种操作模式的单片微处理器上，通过仅使用一个外部引脚连接和用户程序执行，允许从2n种操作模式中选择一种模式的装置。 单片微处理器上的模式设置寄存器可以通过外部引脚进行更新，外部引脚在微处理器的复位状态期间指定作为2n个操作模式的一部分的两种启动模式之一，并且通过执行 在微处理器的正常（非存储）状态期间的用户程序。