公开(公告)号：US06891395B2

公开(公告)日：2005-05-10

申请号：US10853981

申请日：2004-05-25

申请人： Robert W. Wells ,  Zhi-Min Ling ,  Robert D. Patrie ,  Vincent L. Tong ,  Jae Cho ,  Shahin Toutounchi

发明人： Robert W. Wells ,  Zhi-Min Ling ,  Robert D. Patrie ,  Vincent L. Tong ,  Jae Cho ,  Shahin Toutounchi

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G06F17/50 ,  H01L21/82 ,  H03K19/173

CPC分类号： G01R31/318519 ,  G06F17/5054

摘要： Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.

摘要翻译： 公开了利用包含至少一个局部缺陷的可编程逻辑器件的方法。 这些设备被测试以确定它们适用于实现可能不需要受缺陷影响的资源的选定设计。 如果发现FPGA不适合于一个设计，则可以测试其他设计。 在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。 测试电路允许PLD供应商验证PLD对给定用户设计的适用性，而不需要PLD供应商了解用户的设计。

公开(公告)号：US06817006B1

公开(公告)日：2004-11-09

申请号：US10104324

申请日：2002-03-22

申请人： Robert W. Wells ,  Zhi-Min Ling ,  Robert D. Patrie ,  Vincent L. Tong ,  Jae Cho ,  Shahin Toutounchi

发明人： Robert W. Wells ,  Zhi-Min Ling ,  Robert D. Patrie ,  Vincent L. Tong ,  Jae Cho ,  Shahin Toutounchi

IPC分类号： G06F1750

CPC分类号： G01R31/318519

摘要： Disclosed are methods for utilizing programmable logic devices that contain at least one localized defect. Such devices are tested to determine their suitability for implementing selected designs that may not require the resources impacted by the defect. If the FPGA is found to be unsuitable for one design, additional designs may be tested. The test methods in some embodiments employ test circuits derived from a user's design to verify PLD resources required for the design. The test circuits allow PLD vendors to verify the suitability of a PLD for a given user's design without requiring the PLD vendor to understand the user's design.

摘要翻译： 公开了利用包含至少一个局部缺陷的可编程逻辑器件的方法。 这些设备被测试以确定它们适用于实现可能不需要受缺陷影响的资源的选定设计。 如果发现FPGA不适合于一个设计，则可以测试其他设计。 在一些实施例中的测试方法使用从用户设计得出的测试电路来验证设计所需的PLD资源。 测试电路允许PLD供应商验证PLD对给定用户设计的适用性，而不需要PLD供应商了解用户的设计。

公开(公告)号：US06594610B1

公开(公告)日：2003-07-15

申请号：US09853351

申请日：2001-05-11

申请人： Shahin Toutounchi ,  Anthony P. Calderone ,  Zhi-Min Ling ,  Robert D. Patrie ,  Eric J. Thorne ,  Robert W. Wells

发明人： Shahin Toutounchi ,  Anthony P. Calderone ,  Zhi-Min Ling ,  Robert D. Patrie ,  Eric J. Thorne ,  Robert W. Wells

IPC分类号： G06F1900

CPC分类号： G01R31/318519 ,  G01R31/318342

摘要： A new testing method uses a field programmable gate array to emulate faults, instead of using a separate computer to simulate faults. In one embodiment, a few (e.g., two or three) known good FPGAs are selected. A fault is introduced into the design of a FPGA configuration. The configuration is loaded into the FPGAs. A test vector is applied and the result is evaluated. If the result is different from that of a fault-free configuration, the fault is caught. One application of this method is to evaluate fault coverage. A fault model that can be used in the present invention is disclosed.

摘要翻译： 新的测试方法使用现场可编程门阵列来模拟故障，而不是使用单独的计算机来模拟故障。 在一个实施例中，选择几个（例如，两个或三个）已知的良好FPGA。 在FPGA配置的设计中引入了一个故障。 将配置加载到FPGA中。 应用测试向量并评估结果。 如果结果与无故障配置的结果不同，则会发现故障。 这种方法的一个应用是评估故障覆盖。 公开了可用于本发明的故障模型。

公开(公告)号：US06664808B2

公开(公告)日：2003-12-16

申请号：US09924365

申请日：2001-08-07

申请人： Zhi-Min Ling ,  Jae Cho ,  Robert W. Wells ,  Clay S. Johnson ,  Shelly G. Davis

发明人： Zhi-Min Ling ,  Jae Cho ,  Robert W. Wells ,  Clay S. Johnson ,  Shelly G. Davis

IPC分类号： H03K19177

CPC分类号： G01R31/318519

摘要： FPGAs that contain at least one localized defect may be used to implement some designs if the localized defect is not used in the designs. To determine if the FPGA is suitable to implement a design, the design is loaded into the FPGA. The FPGA is tested to determine whether it can execute the design accurately even with the localized defect. The FPGA will be marked as suitable for that design if it passes the test. If the FPGA is found to be unsuitable for one design, additional designs may be tested. Thus, a FPGA manufacturer can sell FPGAs that are normally discarded. As a result, the price of these FPGAs could be set significantly low.

公开(公告)号：US06376131B1

公开(公告)日：2002-04-23

申请号：US09542127

申请日：2000-04-04

申请人： Jae Cho ,  Zhi-Min Ling ,  Xin X. Wu

发明人： Jae Cho ,  Zhi-Min Ling ,  Xin X. Wu

IPC分类号： G03F900

CPC分类号： G03F1/40

摘要： A reticle that is modified to prevent bridging of the masking material (e.g., chrome) between portions of the lithographic mask pattern during an integrated circuit fabrication process. According to a first aspect, the modification involves electrically connecting the various portions of the lithographic mask pattern that balance charges generated in the portions during fabrication processes. In one embodiment, sub-resolution wires that extend between the lithographic mask pattern portions facilitate electrical conduction between the mask pattern portions, thereby equalizing dissimilar charges. In another embodiment, a transparent conductive film is formed over the lithographic mask pattern to facilitate conduction. In accordance with a second aspect, the modification involves separating the various portions of the lithographic mask pattern into relatively small segments by providing sub-resolution gaps between the various portions, thereby minimizing the amount of charge that is generated on each portion.

摘要翻译： 在集成电路制造工艺期间，被修饰以防止掩模材料（例如，铬）桥接在光刻掩模图案的部分之间的掩模版。 根据第一方面，修改涉及电连接平版印刷掩模图案的各个部分，以平衡在制造工艺期间部分中产生的电荷。 在一个实施例中，在光刻掩模图案部分之间延伸的子分辨率线促进掩模图案部分之间的导电，从而均衡不同的电荷。 在另一个实施例中，在光刻掩模图案之上形成透明导电膜以促进传导。 根据第二方面，修改包括通过在各部分之间提供次分辨率间隙将光刻掩模图案的各个部分分离成相对较小的部分，从而最小化在每个部分上产生的电荷量。

公开(公告)号：US5963780A

公开(公告)日：1999-10-05

申请号：US899739

申请日：1997-07-24

申请人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

发明人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

IPC分类号： H01L23/544 ,  H01L21/66 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively silicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.

摘要翻译： 用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置和方法及其制造方法。 实现的是双桥测试结构，其包括第一半导体材料的电阻器路径，例如包括多个条带段和互连段的掺杂硅。 连接具有基本上较低电阻率的多个第二半导体材料带，以形成与相应条带段的并联电路互连。 测试结构通过掩模技术形成，其中规定的掩模区域使得硅电阻器或沉积的多晶硅的部分分别被选择性地硅化以形成硅化物和多硅化物。 用于测试多晶硅层中的缺陷的一个实施例使用聚硅氧烷作为低电阻率带，能够测试开路和短路缺陷。 第二实施例选择性地硅化源极 - 漏极电阻器的暴露部分，从而能够测试金属氧化物半导体的源极 - 漏极层中的缺陷。 通过将测得的电阻值与条的预定宽度和间距进行比较来确定缺陷尺寸。

公开(公告)号：US5716856A

公开(公告)日：1998-02-10

申请号：US517960

申请日：1995-08-22

申请人： Yung-Tao Lin ,  Zhi-Min Ling ,  James Pak ,  Ying Shiau

发明人： Yung-Tao Lin ,  Zhi-Min Ling ,  James Pak ,  Ying Shiau

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  Y10S148/162

摘要： An arrangement and method for detecting sequential processing effects on products to be manufactured in a manufacturing process orders a first set of the products in a first specified processing sequence for a first process step in the manufacturing process. In order to prevent any positional trend created at one process step from being carried over into the next process step, the first set of the products is re-ordered into a second, different specified processing sequence for a second process step in the manufacturing process. Data regarding responses of the first set of the products to the process steps are extracted. The extracted data are correlated with the first and second processing sequences and data analysis is performed on the correlated extracted data. These steps are repeated for subsequent sets of the products, so that although the specified processing sequence is different for each of the individual process steps for a set of products, the same processing sequences for the individual processing steps are used for subsequent sets of the products to be manufactured. Since the processing sequences are not randomized from set to set and do not have to be provided to a database, the amounts of interfacing and disk storage needed are greatly reduced.

公开(公告)号：US07246285B1

公开(公告)日：2007-07-17

申请号：US10815492

申请日：2004-04-01

申请人： Tarek Eldin ,  Zhi-Min Ling ,  Feng Wang ,  David M. Mahoney

发明人： Tarek Eldin ,  Zhi-Min Ling ,  Feng Wang ,  David M. Mahoney

IPC分类号： G01R31/28 ,  G11C29/00

CPC分类号： G01R31/318516 ,  G01R31/31717

摘要： The configuration of a faulty line segment in a switch matrix of a programmable logic device is identified using read-back capture. Each original programmable interconnection point (“PIP”) in the line segment is tested by generating routes from a first logic port through the original line segment and PIP, through all PIPs, adjacent to the original PIP to the opposite logic port. Routes through all PIPs adjacent to the PIPs in the line segment from the first logic port to the second logic port, and from the second logic port to the first logic port, are tested to isolate the fault in the line segment.

摘要翻译： 使用回读捕获识别可编程逻辑器件的开关矩阵中的故障线段的配置。 线段中的每个原始可编程互连点（“PIP”）通过从第一个逻辑端口到原始线段和PIP的路由，通过与原始PIP相邻的所有PIP生成到相对的逻辑端口进行测试。 通过从第一逻辑端口到第二逻辑端口以及从第二逻辑端口到第一逻辑端口的线段中与PIP相邻的所有PIP的路由被测试以隔离线段中的故障。

公开(公告)号：US5821765A

公开(公告)日：1998-10-13

申请号：US900013

申请日：1997-07-24

申请人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

发明人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

IPC分类号： H01L23/544 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively suicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.

摘要翻译： 用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置和方法及其制造方法。 实现的是双桥测试结构，其包括第一半导体材料的电阻器路径，例如包括多个条带段和互连段的掺杂硅。 连接具有基本上较低电阻率的多个第二半导体材料带，以形成与相应条带段的并联电路互连。 测试结构通过掩模技术形成，其中规定的掩模区域使得硅电阻器或沉积的多晶硅的部分分别被选择性地硅化以形成硅化物和多硅化物。 用于测试多晶硅层中的缺陷的一个实施例使用聚硅氧烷作为低电阻率带，能够测试开路和短路缺陷。 第二实施例选择性地使源极 - 漏极电阻器的暴露部分自动化，从而能够测试金属氧化物半导体的源极 - 漏极层中的缺陷。 通过将测得的电阻值与条的预定宽度和间距进行比较来确定缺陷尺寸。

公开(公告)号：US6001663A

公开(公告)日：1999-12-14

申请号：US280997

申请日：1999-03-30

申请人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

发明人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

IPC分类号： H01L23/544 ,  H01L21/66

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively silicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.

摘要翻译： 用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置和方法及其制造方法。 实现的是双桥测试结构，其包括第一半导体材料的电阻器路径，例如包括多个条带段和互连段的掺杂硅。 连接具有基本上较低电阻率的多个第二半导体材料带，以形成与相应条带段的并联电路互连。 测试结构通过掩模技术形成，其中规定的掩模区域使得硅电阻器或沉积的多晶硅的部分分别被选择性地硅化以形成硅化物和多硅化物。 用于测试多晶硅层中的缺陷的一个实施例使用聚硅氧烷作为低电阻率带，能够测试开路和短路缺陷。 第二实施例选择性地硅化源极 - 漏极电阻器的暴露部分，从而能够测试金属氧化物半导体的源极 - 漏极层中的缺陷。 通过将测得的电阻值与条的预定宽度和间距进行比较来确定缺陷尺寸。