公开(公告)号：US20090160032A1

公开(公告)日：2009-06-25

申请号：US12396324

申请日：2009-03-02

申请人： Zing Way Pei ,  Chao An Chung

发明人： Zing Way Pei ,  Chao An Chung

IPC分类号： H01L29/06

CPC分类号： H01L51/0021 ,  H01L27/1292 ,  H01L29/66757 ,  H01L51/0023 ,  H01L51/0541 ,  H01L51/102 ,  H01L2251/105

摘要： An electronic device, e.g., a printed transistor device, comprises a substrate, a first conductive layer, a second conductive layer and a semiconductor layer. The substrate has a first platform and a second platform embossing on the surface thereof, and the first and second platforms are separated by a gap whose width is equivalent to the channel length of the transistor. The first and second conductive layers serving as the source and the drain, respectively, of the transistor device are formed on surfaces of the first and second platforms. The semiconductor layer is formed on the surface of the substrate in the gap.

摘要翻译： 电子器件，例如印刷晶体管器件，包括衬底，第一导电层，第二导电层和半导体层。 衬底具有在其表面上压花的第一平台和第二平台，并且第一和第二平台由宽度等于晶体管的沟道长度的间隙分开。 分别用作晶体管器件的源极和漏极的第一和第二导电层形成在第一和第二平台的表面上。 半导体层形成在间隙的基板的表面上。

公开(公告)号：US20080311713A1

公开(公告)日：2008-12-18

申请号：US12185740

申请日：2008-08-04

申请人： Shin-Chii Lu ,  Yu-Ming Lin ,  Min-Hung Lee ,  Zing-Way Pei ,  Wen-Yi Hsieh

发明人： Shin-Chii Lu ,  Yu-Ming Lin ,  Min-Hung Lee ,  Zing-Way Pei ,  Wen-Yi Hsieh

IPC分类号： H01L21/8238

CPC分类号： H01L29/1054 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate.

摘要翻译： 本发明提供一种互补金属氧化物半导体（CMOS）器件及其制造方法。 CMOSFET器件包括用于PMOSFET的压缩应变SiGe沟道，以及用于NMOSFET的拉伸应变Si沟道，从而分别增强PMOSFET和NMOSFET的空穴和电子迁移率。 因此，可以通过单金属栅极相反对称地获得两种类型的晶体管的阈值电压。

公开(公告)号：US07371628B2

公开(公告)日：2008-05-13

申请号：US11228340

申请日：2005-09-19

申请人： Cha-Hsin Lin ,  Zing-Way Pei ,  Chee-Wee Liu

发明人： Cha-Hsin Lin ,  Zing-Way Pei ,  Chee-Wee Liu

IPC分类号： H01L21/336

CPC分类号： H01L21/823828 ,  H01L21/823807

摘要： A method for fabricating a semiconductor device is provided. The method mainly involves steps of forming at least one first patterned high stress layer below a silicon substrate, then forming a semiconductor device onto the substrate, and forming at least one second patterned high stress layer on the semiconductor device. According to the method, the characteristics of the PMOS and the NMOS transistors formed on the same wafer may be improved simultaneously, by utilizing the stress of the patterned layers of high stress material. Further, the mobility of the carriers is enhanced, so that the output characteristic of the transistors can be improved.

摘要翻译： 提供一种制造半导体器件的方法。 该方法主要包括以下步骤：在硅衬底下方形成至少一个第一图案化的高应力层，然后在衬底上形成半导体器件，并在半导体器件上形成至少一个第二图案化的高应力层。 根据该方法，通过利用高应力材料的图案化层的应力，可以同时改善形成在同一晶片上的PMOS和NMOS晶体管的特性。 此外，载流子的迁移率增强，从而可以提高晶体管的输出特性。

公开(公告)号：US07347228B2

公开(公告)日：2008-03-25

申请号：US11300481

申请日：2005-12-15

申请人： Cha-Hsin Lin ,  Zing-Way Pei ,  Shing-Chii Lu ,  Wen-Yi Hsieh

发明人： Cha-Hsin Lin ,  Zing-Way Pei ,  Shing-Chii Lu ,  Wen-Yi Hsieh

IPC分类号： H01L21/331

CPC分类号： H01L21/823807 ,  H01L21/31155 ,  H01L29/7843

摘要： A method for fabricating semiconductor device is provided. A high stress layer formed on, under or on both sides of the transistors of the semiconductor device is employed as a cap layer. A specific region is then defined through photo resistor mask, and the stress of the region is changed by ion implanting. Therefore, compressive stress and tensile stress occur on the high stress layer. According the disclosed method, the high stress layer may simultaneously improve the characteristics of the transistors formed on the same wafer. Further, the mobility of the carriers of the device is enhanced.

摘要翻译： 提供一种制造半导体器件的方法。 在半导体器件的晶体管的两面上形成的高应力层用作盖层。 然后通过光电阻掩模限定特定区域，并且通过离子注入改变该区域的应力。 因此，在高应力层上产生压缩应力和拉伸应力。 根据所公开的方法，高应力层可以同时改善在同一晶片上形成的晶体管的特性。 此外，装置的载体的移动性增强。

公开(公告)号：US20070059910A1

公开(公告)日：2007-03-15

申请号：US11375337

申请日：2006-03-15

申请人： Zing-Way Pei ,  Peng-Shiu Chen

发明人： Zing-Way Pei ,  Peng-Shiu Chen

IPC分类号： H01L21/3205 ,  H01L21/31 ,  H01L21/336 ,  H01L21/4763 ,  H01L21/8242

CPC分类号： H01L29/513 ,  H01L21/28079 ,  H01L21/28185 ,  H01L29/4958 ,  H01L29/517

摘要： A semiconductor structure and method for manufacturing the same is disclosed. The present invention relates to a semiconductor having a dielectric layer applied on a gate of a transistor, and a high dielectric-coefficient, and a manufacturing method of the semiconductor. Ti is formed on HfO2 to absorb oxygen from the dielectric layer to reduce its thickness, and even make it disappear. However, the TiO2 grown on the layer of Ti advances the growing of HfO2. Simultaneously, the dielectric constant of TiO2 is about 50. The TiO2 substantially enhances the dielectric constant for the dielectric layer. Ti absorbs the oxygen to reduce its thickness and increase the dielectric constant to reduce EOT. Moreover, TiO2 is formed and the dielectric constant is increased after heating. Accordingly, leakage is avoided in the TiO2. The present invention enhances the applications for high-k gate dielectrics with high electric constants, and continuously reduces the EOT.

摘要翻译： 公开了一种半导体结构及其制造方法。 本发明涉及具有施加在晶体管的栅极上的介电层和高介电系数的半导体以及半导体的制造方法。 Ti在HfO 2上形成以从介电层吸收氧气以减小其厚度，甚至使其消失。 然而，在Ti层上生长的TiO 2促进了HfO 2的生长。 同时，TiO 2的介电常数约为50.TiO 2基本上增强了介电层的介电常数。 Ti吸收氧气以减小其厚度并增加介电常数以减少EOT。 此外，形成TiO 2，并且在加热之后介电常数增加。 因此，在TiO 2中避免了泄漏。 本发明增强了具有高电常数的高k栅极电介质的应用，并且连续地降低了EOT。

公开(公告)号：US20060263959A1

公开(公告)日：2006-11-23

申请号：US11228340

申请日：2005-09-19

申请人： Cha-Hsin Lin ,  Zing-Way Pei ,  Chee-Wee Liu

发明人： Cha-Hsin Lin ,  Zing-Way Pei ,  Chee-Wee Liu

IPC分类号： H01L21/8234

CPC分类号： H01L21/823828 ,  H01L21/823807

摘要： A method for fabricating a semiconductor device is provided. The method mainly involves steps of forming at least one first patterned high stress layer below a silicon substrate, then forming a semiconductor device onto the substrate, and forming at least one second patterned high stress layer on the semiconductor device. According to the method, the characteristics of the PMOS and the NMOS transistors formed on the same wafer may be improved simultaneously, by utilizing the stress of the patterned layers of high stress material. Further, the mobility of the carriers is enhanced, so that the output characteristic of the transistors can be improved.

摘要翻译： 提供一种制造半导体器件的方法。 该方法主要包括以下步骤：在硅衬底下方形成至少一个第一图案化的高应力层，然后在衬底上形成半导体器件，并在半导体器件上形成至少一个第二图案化的高应力层。 根据该方法，通过利用高应力材料的图案化层的应力，可以同时改善形成在同一晶片上的PMOS和NMOS晶体管的特性。 此外，载流子的迁移率增强，从而可以提高晶体管的输出特性。

公开(公告)号：US07741169B2

公开(公告)日：2010-06-22

申请号：US12185740

申请日：2008-08-04

申请人： Shin-Chii Lu ,  Yu-Ming Lin ,  Min-Hung Lee ,  Zing-Way Pei ,  Wen Yi Hsieh

发明人： Shin-Chii Lu ,  Yu-Ming Lin ,  Min-Hung Lee ,  Zing-Way Pei ,  Wen Yi Hsieh

IPC分类号： H01L21/8238 ,  H01L21/8234

CPC分类号： H01L29/1054 ,  H01L21/265 ,  H01L21/823807 ,  H01L21/823864 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/78 ,  H01L29/7843 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention provides a complementary metal-oxide-semiconductor (CMOS) device and a fabrication method thereof. The CMOSFET device includes a compressively strained SiGe channel for a PMOSFET, as well as a tensile strained Si channel for an NMOSFET, thereby enhancing hole and electron mobility for the PMOSFET and the NMOSFET, respectively. As such, the threshold voltages of the two types of transistors can be obtained in oppositely symmetric by single metal gate.

摘要翻译： 本发明提供一种互补金属氧化物半导体（CMOS）器件及其制造方法。 CMOSFET器件包括用于PMOSFET的压缩应变SiGe沟道，以及用于NMOSFET的拉伸应变Si沟道，从而分别增强PMOSFET和NMOSFET的空穴和电子迁移率。 因此，可以通过单金属栅极相反对称地获得两种类型的晶体管的阈值电压。

公开(公告)号：US07521305B2

公开(公告)日：2009-04-21

申请号：US11140952

申请日：2005-06-01

申请人： Cha-Hsin Lin ,  Zing-Way Pei ,  Ming-Jinn Tsai ,  Shing-Chii Lu

发明人： Cha-Hsin Lin ,  Zing-Way Pei ,  Ming-Jinn Tsai ,  Shing-Chii Lu

IPC分类号： H01L21/8234

CPC分类号： H01L21/265 ,  H01L21/823807 ,  H01L21/823842 ,  H01L29/78 ,  H01L29/7843

摘要： A method for fabricating a semiconductor device includes the steps of: providing a semiconductor device formed with a plurality of transistors; forming a first stress layer with a plurality of layers on the semiconductor device; forming a second stress layer with a plurality of layers on another surface of the semiconductor device; covering photo resist on a region of the first stress layer to cover at least one of the transistors; and performing ion implantation on the part of the semiconductor device that is not covered by the photo resist. In another embodiment, the second stress layers can be formed after the ion implantation. The method can simultaneously enhance the device performance of the PMOS and NMOS on the same wafer. It also solves the problem of procedure integration caused by the produced compressive stress and tensile stress.

摘要翻译： 一种制造半导体器件的方法包括以下步骤：提供形成有多个晶体管的半导体器件; 在所述半导体器件上形成具有多个层的第一应力层; 在所述半导体器件的另一表面上形成具有多个层的第二应力层; 覆盖所述第一应力层的区域上的光致抗蚀剂以覆盖所述晶体管中的至少一个; 并且对半导体器件的未被光致抗蚀剂覆盖的部分进行离子注入。 在另一个实施例中，可以在离子注入之后形成第二应力层。 该方法可以同时提高同一晶片上的PMOS和NMOS的器件性能。 它也解决了由产生的压缩应力和拉伸应力引起的程序整合问题。

公开(公告)号：US20080068135A1

公开(公告)日：2008-03-20

申请号：US11674151

申请日：2007-02-13

申请人： Chen Pang Kung ,  Zing Way Pei ,  Hung Chun Chen

发明人： Chen Pang Kung ,  Zing Way Pei ,  Hung Chun Chen

IPC分类号： H04Q5/22

CPC分类号： H04B5/00 ,  G06K7/10297 ,  G06K19/0723 ,  H04B5/0031 ,  H04B5/0037 ,  H04B5/0062

摘要： An RFID tag system comprises at least one RFID tag and a reader. The RFID tag outputs a data stream including a head with a plurality of bits set to a sequence of certain levels and a body succeeding the head. The reader can detect the coding frequency of the data stream outputted from the RFID tag according to the known levels in the sequence, and then, read the body data based on the detected frequency.

摘要翻译： RFID标签系统包括至少一个RFID标签和读取器。 RFID标签输出包括头部的数据流，该头部具有被设置为某一级别的序列的多个位和头部后面的身体。 读取器可以根据序列中的已知电平检测从RFID标签输出的数据流的编码频率，然后基于检测到的频率读取主体数据。

公开(公告)号：US20080063983A1

公开(公告)日：2008-03-13

申请号：US11594154

申请日：2006-11-08

申请人： Po-Yuan Lo ,  Feng-Yu Yang ,  Zing-Way Pei

发明人： Po-Yuan Lo ,  Feng-Yu Yang ,  Zing-Way Pei

IPC分类号： G03F7/00

CPC分类号： H01L51/052 ,  Y10S430/106

摘要： A method of fabricating an electronic device is disclosed. The method of fabricating an electronic device comprises providing a substrate. A first conductive layer is formed on the substrate. A silylation polyphenol (PVP) dielectric layer is formed on the first conductive layer. A patterned second conductive layer is formed on the silylation PVP dielectric layer.

摘要翻译： 公开了一种制造电子设备的方法。 制造电子器件的方法包括提供衬底。 在基板上形成第一导电层。 在第一导电层上形成甲硅烷化多酚（PVP）介电层。 在甲硅烷基化PVP介电层上形成图案化的第二导电层。