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公开(公告)号：US20240357254A1
公开(公告)日：2024-10-24
申请号：US18681753
申请日：2022-08-10
发明人： Adi Xhakoni , Scott Johnson , Denver Lloyd
IPC分类号： H04N25/77
CPC分类号： H04N25/77
摘要： In an embodiment a pixel arrangement includes a photodiode, a circuit node, a transfer transistor coupled to the photodiode and to the circuit node, an amplifier with an input coupled to the circuit node, a first capacitor and a second capacitor, a first transistor coupled to an output of the amplifier and to the first capacitor, a second transistor coupled to the first transistor and to the second capacitor, a supply terminal, a reset transistor coupled to the supply terminal, a coupling transistor coupled to the circuit node and to the reset transistor and a third capacitor with a first electrode coupled to a node between the reset transistor and the coupling transistor.
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公开(公告)号：US20240223204A1
公开(公告)日：2024-07-04
申请号：US18557619
申请日：2022-04-27
发明人： Kevin FRONCZAK
CPC分类号： H03M1/1255 , H03M1/002 , H03M1/0668
摘要： Disclosed herein is a ramp circuit for an analogue to digital converter, ADC. The ramp circuit includes a ramp unit configured to provide a ramp signal usable for sampling an analogue signal. The ramp circuit also includes a hold unit connected to the ramp unit, the hold unit is configured to hold a reference voltage for resetting the ramp signal between subsequent samplings of the analogue signal.
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公开(公告)号：US11930288B2
公开(公告)日：2024-03-12
申请号：US17298329
申请日：2019-11-28
发明人： Guy Meynants , Koen Ruythooren , Pieter De Wit
IPC分类号： H04N25/709 , H01L27/146 , H04N25/71 , H04N25/772
CPC分类号： H04N25/709 , H01L27/14612 , H01L27/14643 , H04N25/745 , H04N25/772
摘要： An image sensor comprises an array comprising rows and columns of pixels, a first number N of connection lines connected to a first number N of pixels of the array, a voltage regulating circuit having an output, a first terminal, and a driver circuit. The driver circuit has a first number N of switches coupled to the first number N of connection lines and to the output of the voltage regulating circuit, and a first number N of further switches coupled to the first number N of connection lines and to the first terminal. The first number N is at least two.
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公开(公告)号：US20240053781A1
公开(公告)日：2024-02-15
申请号：US18255109
申请日：2021-11-19
发明人： Carlo FIOCCHI , Federica RESTA , Marco CROCE
摘要： A low-dropout regulator with inrush current limiting capabilities may include an output terminal to provide an output signal, a first current branch comprising a pass device connected to the output terminal, and a second current branch comprising a driver transistor and a current generator. The low-dropout regulator may further include an error amplifier to control the driver transistor. The error amplifier may have a first input node to apply a reference signal, and a second input node coupled to the output terminal. The low-dropout regulator may include a current mirror to couple the second current branch to the first current branch. The current mirror is configured to mirror a current in the second current branch to the output current branch.
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公开(公告)号：US20230276137A1
公开(公告)日：2023-08-31
申请号：US18011777
申请日：2021-06-20
摘要： The present disclosure relates to a processing arrangement for converting digital image data. Conventional approaches suffer from speed or non-ideal compressing schemes. These drawbacks are overcome by the processing arrangement for determining a digital output value from a digital input value based on a linear function and a square root function. The processing arrangement includes a first calculation block configured to determine a first output value of the linear function, a second calculation block configured to determine a second output value of the square root function. A selector is configured to select, based on a comparison between the digital input value and a threshold value, whether the digital output value is determined by the first calculation block or by the second calculation block.
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公开(公告)号：US20220150438A1
公开(公告)日：2022-05-12
申请号：US17440327
申请日：2020-02-05
发明人： Wesley COTTELEER
IPC分类号： H04N5/3745 , H03M1/00 , H04N5/378 , H04N5/376 , H03M1/06
摘要： An analog-to-digital converter for an image sensor comprises a counter circuit to generate a respective counter bit in response to a counter state of the counter circuit, and a storage circuit for storing a respective storage state in response the respective counter bit. The converter further comprises a comparator circuit for generating a level of a comparison signal, and a synchronization circuit to generate a write control signal for controlling the storing of the respective storage state in the respective storage cell. The counter circuit is configured to change the counter state, when a first edge of a cycle of the clock signal is applied to the counter circuit, and to generate the write control signal, when a second edge of the cycle of the clock signal being subsequent to the first edge of the cycle of the clock signal is applied to the synchronization circuit.
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公开(公告)号：US20210235027A1
公开(公告)日：2021-07-29
申请号：US17264668
申请日：2019-07-17
发明人： Guy MEYNANTS
IPC分类号： H04N5/353 , H04N5/378 , H04N5/3745
摘要： A pixel cell includes a pixel set with a plurality of pixels, with each pixel of the pixel set being configured to capture optical information incident upon the respective pixel and generate electrical information representative of the optical information. The pixel cell further includes a readout circuit which is configured to manage collection and output of the electrical information from each pixel of the pixel set and to operate the pixel set in a global shutter mode and in a rolling shutter mode of operation. In the global shutter mode, the electrical information from each pixel is combined for generating a global shutter output signal, while in the rolling shutter mode, the electrical information from each pixel is used to generate individual rolling shutter output signals.
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公开(公告)号：US10348323B2
公开(公告)日：2019-07-09
申请号：US15773537
申请日：2016-10-27
发明人： Adi Xhakoni , Tim Blanchaert , Guy Meynants
摘要： An analog-to-digital converter (110) comprises an analog signal input (122) for receiving an analog signal and an amplifying stage (160) configured to generate a set of N amplified analog signals, where N is an integer ≥2. The set of N signals have different gains. The ADC has a ramp signal input (121) for receiving a ramp signal and a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the set of amplified analog signals (SigG1, SigG2) and to the ramp signal input (121). The comparison stage (120) is configured to compare the amplified analog signals with the ramp signal to provide comparison outputs during a conversion period. A control stage is configured to control the counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.
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公开(公告)号：US10340936B2
公开(公告)日：2019-07-02
申请号：US15773149
申请日：2016-10-27
发明人： Adi Xhakoni , Tim Blanchaert
摘要： An analog-to-digital converter (110) for an imaging device comprises an analog signal input (123) for receiving an analog signal from a pixel array of the imaging device and N ramp signal inputs (121, 122) for receiving N ramp signals, where N is an integer ≥2. The N ramp signals have different slopes. The ADC has a clock input (143) for receiving at least one clock signal. A comparison stage (120) is connected to the ramp signal inputs and to the analog signal input. The comparison stage (120) is configured to compare the ramp signals with the analog signal to provide comparison outputs during the conversion period. A control stage (130) is configured to control a counter stage (140) based on the comparison outputs and a selection input indicative of when at least one handover point has been reached during the conversion period.
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公开(公告)号：US12022203B2
公开(公告)日：2024-06-25
申请号：US18011777
申请日：2021-06-22
摘要： The present disclosure relates to a processing arrangement for converting digital image data. Conventional approaches suffer from speed or non-ideal compressing schemes. These drawbacks are overcome by the processing arrangement for determining a digital output value from a digital input value based on a linear function and a square root function. The processing arrangement includes a first calculation block configured to determine a first output value of the linear function, a second calculation block configured to determine a second output value of the square root function. A selector is configured to select, based on a comparison between the digital input value and a threshold value, whether the digital output value is determined by the first calculation block or by the second calculation block.
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