公开(公告)号：US20140181457A1

公开(公告)日：2014-06-26

申请号：US13725305

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lisa R. HSU ,  Gabriel H. LOH ,  Michael IGNATOWSKI ,  Michael J. SCHULTE ,  Nuwan S. JAYASENA ,  James M. O'CONNOR

IPC: G06F12/10

CPC classification number: G06F12/10 ,  G06F11/1666 ,  G06F11/2094

Abstract: A system, method, and memory device embodying some aspects of the present invention for remapping external memory addresses and internal memory locations in stacked memory are provided. The stacked memory includes one or more memory layers configured to store data. The stacked memory also includes a logic layer connected to the memory layer. The logic layer has an Input/Output (I/O) port configured to receive read and write commands from external devices, a memory map configured to maintain an association between external memory addresses and internal memory locations, and a controller coupled to the I/O port, memory map, and memory layers, configured to store data received from external devices to internal memory locations.

Abstract translation: 提供体现本发明的一些方面的用于重新映射外部存储器地址和堆叠存储器中的内部存储器位置的系统，方法和存储器件。 堆叠的存储器包括被配置为存储数据的一个或多个存储器层。 堆叠的存储器还包括连接到存储器层的逻辑层。 逻辑层具有被配置为从外部设备接收读取和写入命令的输入/输出（I / O）端口，被配置为保持外部存储器地址和内部存储器位置之间的关联的存储器映射以及耦合到I / O端口，内存映射和内存层，配置为将从外部设备接收的数据存储到内部存储器位置。

公开(公告)号：US20160055005A1

公开(公告)日：2016-02-25

申请号：US14466080

申请日：2014-08-22

Applicant: Advanced Micro Devices, Inc.

Inventor： Lisa R. HSU ,  James Michael O'Connor

IPC: G06F9/38 ,  G06F15/80 ,  G06F9/32

CPC classification number: G06F9/3887 ,  G06F12/1027 ,  G06F2212/654

Abstract: Embodiments disclose a system and method for reducing virtual address translation latency in a wide execution engine that implements virtual memory. One example method describes a method comprising receiving a wavefront, classifying the wavefront into a subset based on classification criteria selected to reduce virtual address translation latency associated with a memory support structure, and scheduling the wavefront for processing based on the classifying.

Abstract translation: 实施例公开了一种在实现虚拟存储器的宽执行引擎中减少虚拟地址转换等待时间的系统和方法。 一个示例性方法描述了一种方法，包括接收波阵面，基于所选择的分类标准将波阵面分类为子集，以减少与存储器支持结构相关联的虚拟地址转换延迟，以及基于分类调度波阵面进行处理。

公开(公告)号：US20140181453A1

公开(公告)日：2014-06-26

申请号：US13721395

申请日：2012-12-20

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Nuwan S. JAYASENA ,  Gabriel H. LOH ,  Bradford M. BECKMANN ,  James M. O'CONNOR ,  Lisa R. HSU

IPC: G06F3/06 ,  G11C5/06

CPC classification number: G11C5/06 ,  G06F12/02 ,  G06F12/10 ,  G06F13/1694 ,  G11C7/1006

Abstract: A system, method, and computer program product are provided for a memory device system. One or more memory dies and at least one logic die are disposed in a package and communicatively coupled. The logic die comprises a processing device configurable to manage virtual memory and operate in an operating mode. The operating mode is selected from a set of operating modes comprising a slave operating mode and a host operating mode.

Abstract translation: 为存储器件系统提供了一种系统，方法和计算机程序产品。 一个或多个存储器管芯和至少一个逻辑管芯设置在封装中并且通信耦合。 逻辑管芯包括可配置为管理虚拟存储器并以操作模式操作的处理设备。 从包括从动操作模式和主机操作模式的一组操作模式中选择操作模式。