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    Providing interrupts from an input-output memory management unit to guest operating systems
    3.
    发明授权
    Providing interrupts from an input-output memory management unit to guest operating systems 有权

    公开(公告)号：US11042495B2

    公开(公告)日：2021-06-22

    申请号：US16578165

    申请日：2019-09-20

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Maggie Chan ,  Philip Ng ,  Paul Blinzer

    IPC: G06F13/24 ,  G06F9/455 ,  G06F13/16

    Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.

    DYNAMIC ADJUSTMENT OF MEMORY OPERATING FREQUENCY TO AVOID RF INTERFERENCE WITH WIFI
    5.
    发明公开
    DYNAMIC ADJUSTMENT OF MEMORY OPERATING FREQUENCY TO AVOID RF INTERFERENCE WITH WIFI 审中-公开

    公开(公告)号：US20240334340A1

    公开(公告)日：2024-10-03

    申请号：US18128805

    申请日：2023-03-30

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Paul Blinzer ,  Chirag Nitinkumar Dhruv ,  Ranjeet Kumar ,  Gia Tung Phan ,  Ashish Jain

    IPC: H04W52/02

    CPC classification number: H04W52/029 ,  H04W52/0274

    Abstract: An apparatus and method for efficiently performing power management for increasing reliable wireless signal transfer performed by mobile computing devices. In various implementations, a computing system includes a network interface and multiple components for processing tasks. The network interface sends, to at least a given component of the multiple components, an indication specifying the corresponding operating frequency ranges used by one or more radio modules used for wireless communication with an access point. The given component determines whether an operating clock frequency of the given component overlaps any of the received operating frequency ranges and associated harmonic frequencies. If so, then the given component changes the operating clock frequency to a frequency that does not overlap any of the received operating frequency ranges and associated harmonic frequencies.

    Method and apparatus for integration of non-volatile memory
    6.
    发明授权
    Method and apparatus for integration of non-volatile memory 有权

    公开(公告)号：US10761736B2

    公开(公告)日：2020-09-01

    申请号：US16055716

    申请日：2018-08-06

    Applicant: ATI Technologies ULC ,  ADVANCED MICRO DEVICES, INC.

    Inventor： Nima Osqueizadeh ,  Paul Blinzer

    IPC: G06F3/06

    Abstract: Described herein is a method and system for directly accessing and transferring data between a first memory architecture and a second memory architecture associated with a graphics processing unit (GPU) by treating the first memory architecture, the second memory architecture and system memory as a single physical memory, where the first memory architecture is a non-volatile memory (NVM) and the second memory architecture is a local memory. Upon accessing a virtual address (VA) range by a processor, the requested content is paged in from the single physical memory and is then redirected by a virtual storage driver to the second memory architecture or the system memory, depending on which of the GPU or CPU triggered the access request. The memory transfer occurs without awareness of the application and the operating system.

    Networked input/output memory management unit
    9.
    发明授权
    Networked input/output memory management unit 有权

    公开(公告)号：US11003588B2

    公开(公告)日：2021-05-11

    申请号：US16548692

    申请日：2019-08-22

    Applicant: ADVANCED MICRO DEVICES, INC. ,  ATI TECHNOLOGIES ULC

    Inventor： Sonu Arora ,  Paul Blinzer ,  Philip Ng ,  Nippon Harshadk Raval

    IPC: G06F3/06 ,  G06F12/1027 ,  G06F13/16

    Abstract: A networked input/output memory management unit (IOMMU) includes a plurality of IOMMUs. The networked IOMMU receives a memory access request that includes a domain physical address generated by a first address translation layer. The networked IOMMU selectively translates the domain physical address into a physical address in a system memory using one of the plurality of IOMMUs that is selected based on a type of a device that generated the memory access request. In some cases, the networked IOMMU is connected to a graphics processing unit (GPU), at least one peripheral device, and the memory. The networked IOMMU includes a command queue to receive the memory access requests, a primary IOMMU to selectively translate the domain physical address in memory access requests from the GPU, and a secondary IOMMU to translate the domain physical address in memory requests from the peripheral device.

    Providing Interrupts from an Input-Output Memory Management Unit to Guest Operating Systems
    10.
    发明申请
    Providing Interrupts from an Input-Output Memory Management Unit to Guest Operating Systems 有权

    公开(公告)号：US20210089480A1

    公开(公告)日：2021-03-25

    申请号：US16578165

    申请日：2019-09-20

    Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

    Inventor： Maggie Chan ,  Philip Ng ,  Paul Blinzer

    IPC: G06F13/24 ,  G06F13/16 ,  G06F9/455

    Abstract: An electronic device includes a processor that executes a guest operating system; a memory having a guest portion that is reserved for storing data and information to be accessed by the guest operating system; and an input-output memory management unit (IOMMU). The IOMMU performs operations for signaling an interrupt to the guest operating system. For these operations, the IOMMU acquires, from an entry in an interrupt remapping table associated with the guest operating system, a location in a virtual advanced programmable interrupt controller (APIC) backing page for the guest operating system in the guest portion of the memory. The IOMMU then writes information about the interrupt to the location in the virtual APIC backing page. The IOMMU next communicates an indication of the interrupt to the guest operating system.

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