公开(公告)号：US20110127529A1

公开(公告)日：2011-06-02

申请号：US12627343

申请日：2009-11-30

申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： H01L27/12 ,  H01L21/762

CPC分类号： H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 可选地，在该相同部分内形成微腔，以便平衡由于掺杂增加导致的电导率的增加，同时具有相应的电阻率增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于形成这种半导体结构的方法的实施例。

公开(公告)号：US08492868B2

公开(公告)日：2013-07-23

申请号：US12848558

申请日：2010-08-02

申请人： Alan B. Botula ,  Alvin J. Joseph ,  James A. Slinkman ,  Randy L. Wolf

发明人： Alan B. Botula ,  Alvin J. Joseph ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/0211 ,  H01L27/0617 ,  H01L27/1203

摘要： A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.

摘要翻译： 一种方法，集成电路和设计结构包括具有沟槽结构的硅衬底层和离子杂质植入物。 绝缘体层位于硅衬底层上并接触硅衬底层。 绝缘体层填充沟槽结构。 电路层位于掩埋绝缘体层上并与其接触。 电路层包括由被动结构分开的一组有源电路。 当从顶视图观察集成电路结构时，沟槽结构位于有源电路组之间。 因此，当从顶视图观察集成电路结构时，沟槽结构在被动结构之下并且不在电路组下方。

公开(公告)号：US20120025345A1

公开(公告)日：2012-02-02

申请号：US12848558

申请日：2010-08-02

申请人： ALAN B. BOTULA ,  Alvin J. Joseph ,  James A. Slinkman ,  Randy L. Wolf

发明人： ALAN B. BOTULA ,  Alvin J. Joseph ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： H01L29/06 ,  H01L21/762

CPC分类号： H01L21/76283 ,  H01L21/84 ,  H01L27/0211 ,  H01L27/0617 ,  H01L27/1203

摘要： A method, integrated circuit and design structure includes a silicon substrate layer having trench structures and an ion impurity implant. An insulator layer is positioned on and contacts the silicon substrate layer. The insulator layer fills the trench structures. A circuitry layer is positioned on and contacts the buried insulator layer. The circuitry layer comprises groups of active circuits separated by passive structures. The trench structures are positioned between the groups of active circuits when the integrated circuit structure is viewed from the top view. Thus, the trench structures are below the passive structures and are not below the groups of circuits when the integrated circuit structure is viewed from the top view.

摘要翻译： 一种方法，集成电路和设计结构包括具有沟槽结构的硅衬底层和离子杂质植入物。 绝缘体层位于硅衬底层上并接触硅衬底层。 绝缘体层填充沟槽结构。 电路层位于掩埋绝缘体层上并与其接触。 电路层包括由被动结构分开的一组有源电路。 当从顶视图观察集成电路结构时，沟槽结构位于有源电路组之间。 因此，当从顶视图观察集成电路结构时，沟槽结构在被动结构之下并且不在电路组下方。

公开(公告)号：US08698244B2

公开(公告)日：2014-04-15

申请号：US12634893

申请日：2009-12-10

申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： H01L27/12

CPC分类号： H01L29/78603 ,  H01L21/84 ,  H01L27/1203

摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 任选地，在该相同部分内形成微腔，以平衡电导率的任何增加和电阻率的相应增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于这种半导体结构的方法和设计结构的实施例。

公开(公告)号：US08471340B2

公开(公告)日：2013-06-25

申请号：US12627343

申请日：2009-11-30

申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： H01L21/70

CPC分类号： H01L21/02488 ,  H01L21/2652 ,  H01L21/7624 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/78603

摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity due to increased doping with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method for forming such a semiconductor structure.

公开(公告)号：US20110131542A1

公开(公告)日：2011-06-02

申请号：US12634893

申请日：2009-12-10

申请人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

发明人： Alan B. Botula ,  John J. Ellis-Monaghan ,  Alvin J. Joseph ,  Max G. Levy ,  Richard A. Phelps ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： G06F17/50

CPC分类号： H01L29/78603 ,  H01L21/84 ,  H01L27/1203

摘要： Disclosed is semiconductor structure with an insulator layer on a semiconductor substrate and a device layer is on the insulator layer. The substrate is doped with a relatively low dose of a dopant having a given conductivity type such that it has a relatively high resistivity. Additionally, a portion of the semiconductor substrate immediately adjacent to the insulator layer can be doped with a slightly higher dose of the same dopant, a different dopant having the same conductivity type or a combination thereof. Optionally, micro-cavities are created within this same portion so as to balance out any increase in conductivity with a corresponding increase in resistivity. Increasing the dopant concentration at the semiconductor substrate-insulator layer interface raises the threshold voltage (Vt) of any resulting parasitic capacitors and, thereby reduces harmonic behavior. Also disclosed herein are embodiments of a method and a design structure for such a semiconductor structure.

摘要翻译： 公开了在半导体衬底上具有绝缘体层并且器件层位于绝缘体层上的半导体结构。 衬底掺杂有相对低剂量的具有给定导电类型的掺杂剂，使得其具有相对高的电阻率。 此外，与绝缘体层紧密相邻的半导体衬底的一部分可掺杂略高的相同掺杂剂剂量，具有相同导电类型的不同掺杂剂或其组合。 任选地，在该相同部分内形成微腔，以平衡电导率的任何增加和电阻率的相应增加。 增加半导体衬底 - 绝缘体层界面处的掺杂剂浓度会提高任何结果的寄生电容器的阈值电压（Vt），从而降低谐波行为。 本文还公开了用于这种半导体结构的方法和设计结构的实施例。

公开(公告)号：US09070651B2

公开(公告)日：2015-06-30

申请号：US13309829

申请日：2011-12-02

申请人： Alan B. Botula ,  Alvin J. Joseph ,  Randy L. Wolf

发明人： Alan B. Botula ,  Alvin J. Joseph ,  Randy L. Wolf

IPC分类号： G06F17/50 ,  H01L27/06 ,  H01L21/66 ,  G01R31/28

CPC分类号： H01L22/34 ,  G01R31/2884 ,  G06F17/5063 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

摘要： A non-linear kerf monitor, methods of manufacture and design structures are provided. The structure includes a coplanar waveguide provided in a kerf of a wafer between a first chip and a second chip. The structure further includes a shunt switch and a series switch coupled to the coplanar waveguide.

摘要翻译： 提供非线性切口监视器，制造方法和设计结构。 该结构包括设置在第一芯片和第二芯片之间的晶片的切口中的共面波导。 该结构还包括耦合到共面波导的分流开关和串联开关。

公开(公告)号：US08299537B2

公开(公告)日：2012-10-30

申请号：US12369099

申请日：2009-02-11

申请人： Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

发明人： Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： H01L21/70

CPC分类号： H01L21/7624 ,  H01L21/26506 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure.

摘要翻译： 绝缘体上半导体衬底和相关半导体结构以及绝缘体上半导体衬底和相关半导体结构的制造方法提供了一种位于并形成在基底半导体内的多阶射频谐波抑制区域 在绝缘体上半导体衬底内的掩埋介质层与基底半导体衬底的界面下方的位置处的衬底。 多级射频谐波抑制区域可以包括离子注入原子，例如但不限于稀有气体原子，以在对射频设备供电时提供抑制的多阶射频谐波，例如但不限于无线电 位于和形成在半导体结构内的表面半导体层内和之上的高频互补金属氧化物半导体器件（或替代地，无源器件）。

公开(公告)号：US08492294B2

公开(公告)日：2013-07-23

申请号：US13608314

申请日：2012-09-10

申请人： Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

发明人： Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： H01L21/00

CPC分类号： H01L21/7624 ,  H01L21/26506 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure.

摘要翻译： 绝缘体上半导体衬底和相关半导体结构以及绝缘体上半导体衬底和相关半导体结构的制造方法提供了一种位于并形成在基底半导体内的多阶射频谐波抑制区域 在绝缘体上半导体衬底内的掩埋介质层与基底半导体衬底的界面下方的位置处的衬底。 多级射频谐波抑制区域可以包括离子注入原子，例如但不限于稀有气体原子，以在对射频设备供电时提供抑制的多阶射频谐波，例如但不限于无线电 位于和形成在半导体结构内的表面半导体层内和之上的高频互补金属氧化物半导体器件（或替代地，无源器件）。

公开(公告)号：US20130005157A1

公开(公告)日：2013-01-03

申请号：US13608314

申请日：2012-09-10

申请人： Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

发明人： Joseph R. Greco ,  Kevin Munger ,  Richard A. Phelps ,  Jennifer C. Robbins ,  William Savaria ,  James A. Slinkman ,  Randy L. Wolf

IPC分类号： H01L21/265

CPC分类号： H01L21/7624 ,  H01L21/26506 ,  H01L21/84 ,  H01L27/1203

摘要： A semiconductor-on-insulator substrate and a related semiconductor structure, as well as a method for fabricating the semiconductor-on-insulator substrate and the related semiconductor structure, provide for a multiple order radio frequency harmonic suppressing region located and formed within a base semiconductor substrate at a location beneath an interface of a buried dielectric layer with the base semiconductor substrate within the semiconductor-on-insulator substrate. The multiple order radio frequency harmonic suppressing region may comprise an ion implanted atom, such as but not limited to a noble gas atom, to provide a suppressed multiple order radio frequency harmonic when powering a radio frequency device, such as but not limited to a radio frequency complementary metal oxide semiconductor device (or alternatively a passive device), located and formed within and upon a surface semiconductor layer within the semiconductor structure.

摘要翻译： 绝缘体上半导体衬底和相关半导体结构以及绝缘体上半导体衬底和相关半导体结构的制造方法提供了一种位于并形成在基底半导体内的多阶射频谐波抑制区域 在绝缘体上半导体衬底内的掩埋介质层与基底半导体衬底的界面下方的位置处的衬底。 多级射频谐波抑制区域可以包括离子注入原子，例如但不限于稀有气体原子，以在对射频设备供电时提供抑制的多阶射频谐波，例如但不限于无线电 位于和形成在半导体结构内的表面半导体层内和之上的高频互补金属氧化物半导体器件（或替代地，无源器件）。